Semiconductor IP News and Trends Blog

EDA Survives Export Control, Thanks to a Few

A few EDAC export-control experts save the EDA industry from potentially devastating technology, IP, and encryption regulations.

A few nights ago, I learned about a new breed of EDA industry heroes. They are not the brilliant mathematicians, physicists, or engineers who create elegant and highly efficient algorithms. Nor are they the system architects who integrate complex tool flows.

The heroes I mention are the professionals who have waded into the murky waters of government bureaucracy, legal processes, special-interest lobbyists, and politicians to keep EDA technology as free from red tape as possible. I refer to the few, the proud, the “export-control” specialists.

One such champion is Larry Disenhof, Cadence’s Group Director, Export Compliance and Government Relations and Chairman of the EDAC Export Committee.  Last month, I interviewed Disenhof concerning the importance of export control. This interview was a prelude to a recent webinar in which Disenhof examined the current state of export regulations and their effect on the EDA community. What follows are just a few highlights from that tutorial:

• There are three pillars for successful navigation of technology export control: 1) Check your product’s classification, 2) Check the country of destination for your product, and 3) Check the end user.
• Here’s a vital government reference for developing an export management system and creating a compliance program.
• Pay attention to definitions, especially familiar ones like software, hardware, and technology (see Figure 1). The good news is that EDA tools fit under the definition of technology: “Specific information necessary for the development, production, or use of a product. The information takes the form of technical data or technical assistance.” This includes IP, libraries, training, and installation, operation, maintenance, and repair (see Commerce Control List Categories).
• It’s hard to guess what may or may not be restricted or controlled. For example, electronic vacuum tubes are controlled if they operate above 31.8 GHz and are ““allocated by the ITU” for radio-communications services, but not for radio determination.” Why is 31.8 GHz a cut-off parameter? Probably because that frequency and above are part of NASA’s Deep Space Network (DSN), which is an international network of antennas that supports interplanetary spacecraft missions and radio and radar astronomy observations (see Computational Powerhouse Hidden In Island Jungle).

Figure 1: Every word in the export-control documents has a specific meaning. Cat3 refers to electronics, part of the commerce control list.

• While it may seem a painful experience, engineers have to determine precisely where their designs (products) fit.  The best approach is to follow the guidelines provided on the government web site.
• EDA software fits under category 3D991. Note that “unrestricted” does not mean “uncontrolled” (see Figure 2).

Figure 2: While EDA software is unrestricted, it is not uncontrolled.

• Unrestricted IP (3E991 or EAR99) refers to the following: DDR and similar memory controllers; USB, PCIe, and similar connectors; and system bus structures.
• Controlled IP (3A001/3E001) includes certain analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field-programmable gate arrays (FPGAs, believe it or not)! The devil is in the details (e.g., controlled IP includes FPGAs that have single-ended digital input/outputs of 500 or greater or an aggregate one-way peak serial-transceiver data rate of 200 Gb/s or greater).
• ADCs and DACs are on the controlled list because they can be used in benign products like TV remotes or less-benign applications like missile launch controls. This is why companies must screen the end users/customers of their technology and products.
• Another example of restricted and controlled IP use is found in FPGA applications. More and more companies are putting their semiconductor IP into FGPAs and then sending the FPGA system to customers. But FPGAs are restricted because customers can reconfigure an FPGA for unintended applications, like missile technology.
• What about semiconductor manufacturing equipment, defined as CAT3 Hardware: 3B001? Even though the government knows which countries own these machines, the equipment is still considered restricted. However, EDA software is not restricted.
• Is leading-edge process-node technology restricted or controlled (e.g, 20 nm)? According to Disenhof, the only place where process-node technology might be covered is in the 3E002 related section about “line width tech.” However, the regulations do not control “technology” for the development or production of ICs (as defined in other sections) at or above 0.130 nm and incorporating three or fewer metal layers. (I’m not sure that statement makes the true intention any clearer.)
• One of the keys/pillars to understanding what is controlled is knowing the end purpose of the technology. For example, designing memory chips is okay, but control chips are another matter.
• Encryption: The EDA community should be extremely grateful that it doesn’t have to deal with this issue. The EDA heroes who I mentioned earlier helped to mitigate the very restricted regulation on encryption, as shown with this key position allowing encryption for EDA applications: “Encryption and/or decryption for protection of libraries, design attributes, or associated data for the design of semi devices and ICs.”
• “This is probably the biggest, best thing that happened to EDA,” said Disenhof. “Naturally, it’s a different matter if you are designing IP to actually do encryption.”