Delay Locked Loops (DLL) are timing circuits that are used to eliminate propagation delay and clock skew between output clock signals on the device.
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Other IP includes many additional types of Embedded I/O Cores IP
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PHY IP provides the physical layer of the OSI model, which connects a link layer device to the physical medium
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Phase Locked Loops (PLL) are timing circuits that generate output signals that are phase-related to a reference signal, which keeps the phases of the two signals matched.
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Serializer/Deserializer (SERDES) technology is used in high speed applications to convert data between serial and parallel data interfaces
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