Semiconductor IP News and Trends Blog

Forte’s Acquisition Highlights Need for Models and IP

The high-level synthesis market for ASIC and FPGA designs just got more interesting with Cadence’s acquisition of Forte. But what about the models and IP?

The relatively quiet high-level-synthesis (HLS) community was awoken this week by news of Cadence’s intention to acquire Forte Design. Does this acquisition portent changes on the modeling and intellectual-property (IP) integration front?

I’m exploring these questions with industry experts, but that story is not yet complete. What is known is that high-level synthesis (HLS) is vital for ASIC and FGPA designers as they interface with the system-on-a-chip (SoC) system architects. These HLS tools follow the electronic-system-level (ESL) methodology to provide the high-level power and performance tradeoffs necessary to move a design from the behavioral to partitioned architectural levels. To be specific, HLS transforms behavioral C++ models into untimed Verilog RTL.

But as Gary Smith warns, ESL is not a software process, as the end result is the creation of hardware. “Do not consider behavioral ESL design as software; it’s modeling.” That is why Smith’s big message to the EDA tool companies at last year’s DAC was, “Give away the (ESL) tools if you must, but sell the models.”

Indeed, the models and the related IP are bringing attention to the Forte acquisition. How will Cadence work these assets from Forte into both its existing HLS “C-to-Silicon” tool as well as its EDA360 vision for SoC development and beyond. For now, though, the acquisition seems to signify an important move for the HLS community. Further, Smith sees it as “a good sign of Cadence’s renewed presence in the EDA market.”