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Overview
Today, links such as PCI Express, HDMI, USB are ubiquitous. But it wasn’t always that way. The last 20 years have seen an explosion in the number of serial link applications. In this two-part series, we will explore why serial links (and the SERDES that enable them) have become so popular. We will attempt to explain some of the underlying technology that makes serial links ubiquitous, and why that wasn’t the case 20 years go.
My career began in the late 1990s, just before the SERDES revolution. In this article, I’ll show examples of some of the SERDES I’ve worked on and use these examples to help explain the progress that the design and technology communities have made in the last two decades.
Reasons for serialization (Why do we need SERDES?)
Origins and Evolution
SERDES have their background in communication over fiber optic and coaxial links. The reason for this is quite obvious of course – sending bytes serially rather than in parallel limits the number of cables! With one or only a few cables, maximizing the throughput over the cable was most important. The SERDES area and power were secondary considerations.
In the mid 1980s, the data rate of serial links was driven in large part by telecom requirements (SONET). During this period, the requirements for OC-1 and OC-3 were modest by today’s standards (51.84 Mbps, 155.52Mbps). OC-24 required a line rate above 1Gbps (1244.16 Mbps) which was supported by state-of-the-art circuits around 1990 in Bipolar and GaAs processes.
My career began in the late 1990s. Fortunately for me, this coincided with an important time in the history of SERDES. At this time, OC-24 (2488.32Mbps) was available and people were planning OC-192 at approximately 10Gbps. A few years later (early 2000s), 10Gb Ethernet via a 10Gb/s line rate became real (as opposed to XAUI where 4 channels were used for 10Gb/s aggregate).
Another important development was beginning - SERDES were being used more and more for chip-to-chip communication on PCBs and backplanes to replace parallel links. This development would turn SERDES from an important long-distance communications circuit into a critical SoC component. Perhaps the most important example of this is PCIe, which was introduced around 2002 at 2.5Gbps and became popular in the mid-2000s.
The following set of plots show the rollout of various serial data standards and the state of SERDES research. These serial standards are shown above in Figure 1.
- Optical Transmission
- OC-192, OC-768, SONET
- Internal PC
- PCIe 1-5
- Storage
- Fibre Channel, SATA, SAS
- Serial Bus
- USB, Thunderbolt
- Video Display
- DisplayPort, HDMI
- Networking
- SGMII, 1Gb Ethernet, 10Gb Ethernet, 25/100Gb Ethernet
As would be expected, line rate has been increasing at an exponential rate. The same effect can be seen across category, with optical transmission leading the other categories following. This plot only contains NRZ (PAM2) standards. PAM4 standards are emerging at line rates around 50Gbps.
To understand the circuit-level innovations enabling the SERDES evolution, I’ve queried International Solid State Circuits Conference (ISSCC) publications using IEEE’s Xplore Digital Library, generating a list of ISSCC publications covering “Clock and Data Recovery” and “SERDES”. The data set is then broken down by:
- Technology type:
- CMOS
- Not CMOS (Bipolar, BiCMOS, HBT, etc.)
- Geometry
- 65nm, 40nm, 7nm, etc.
- Signalling
- PAM2, PAM4
- Organization publishing
- Industrial, Academic
Using this data set, the line rate is plotted against the publication year. It is estimated that the circuits are designed roughly one year ahead of publication. However, industrial applications following from these publications could trail the publication by several years.
The plot shows that Bipolar, BiCMOS, and HBT technologies were widely published before 2005, but rarely published following 2005. These pre-2005 publications were describing technologies that drove optical networking applications where line rate was most important, and power/form-factor/integration were secondary considerations.
For SERDES applications with much higher volumes such as PC, Storage, Video Display, and Networking, the key isn’t line rate alone. The important factors become cost, power, form-factor, and integration with large digital cores!
The following plot is generated by sorting the ISSCC data by Academic and Industrial publications, and by NRZ/PAM2 vs PAM4 signaling.
A correlation can be seen between the CMOS geometry and the line rate. For example, below 90nm, most publications were greater than 10Gbps. Also, PAM4 systems were not commonly developed or published above 28nm due to the high level of integration (ADCs, DSPs) needed beyond an NRZ/PAM2 SERDES and the high bandwidth requirements of the CMOS technology.
There is a noticeable lack of PAM4 publications among academic institutions. This is partially due to the search criteria used. There are academic publications related to PAM4 components, but very few full PAM4 transceivers done by academics. One possible explanation for this is the large complexity of a PAM4 system (ADCs, DACs, DSP, PLLs, CDRs, etc.). Another possible explanation is the cost of and access to advanced CMOS geometries such as 7nm and 14/16nm.
Combining the datasets for serial link publications and serial data rate standards leads to the following plot.
From the plot above, the advanced CMOS circuit design publications at ISSCC have lead the high volume serial data standards in network to display by several years. PAM2 CMOS research has made possible PCIe1 through PCIe5 (at 32Gbps), 28Gbps Ethernet line rates, and more.
Pin Count and Channel Advantage
The most obvious advantages of SERDES are a reduction in pin count and cable / channel count.
For early SERDES, this meant bytes of data could be sent across a coax or a fiber.
For modern SERDES, another advantage is being able to send bytes of data over a pair of differential signal pins rather than 8, 16, 32, or N data pins and a clock pin. This aspect of serialization leads to cost savings due to smaller packages and denser PCBs. The specifics of the advantages depend on die cost, package cost, PCB cost, PCB congestion, and other factors.
Distance Advantage
In the past decade, the ability of SERDES to transmit long distances across PCBs and backplanes has helped them reach many new areas.
From basic microwave design, we know that a transmission line looks like a “lumped element” when the time of flight is less than the rise/fall time. For a parallel interface with GPIOs, the rise/fall times are typically no less than several nano-seconds. This sets the distance a parallel unterminated interface can operate to about 30cm on a typical PCB. Terminating a parallel bus would increase the reach but add a huge amount of power and make the power efficiency drastically worse.
SERDES interfaces are typically transmitting across controlled impedance transmission lines where both ends (TX, RX) are terminated. This allows the bits to be transmitted rapidly without concern for reflections. Of course, to transmit rapidly and serially, a lot of extra complexity is involved – serializers, de-serializers, TX PLLs, RX CDRs, Feed-Forward Equalization, Receive Equalization, etc.
(In part two, we’ll explore the power advantages of SERDES, how I’ve observed the technology’s evolution and what challenges lie ahead for future development.)
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- Multiprotocol Wirebond 2-lane SerDes PMA - 0.25Gbps to 8.1Gbps
- Multiprotocol 4-lane SerDes PMA - 0.125Gbps to 16Gbps
- Chip-Chip SerDes 1-lane PMA - 1.25Gbps to 5.0Gbps wirebond
