Semiconductor IP News and Trends Blog
Ghost of Semiconductor Predictions Past
What lies ahead for the world of semiconductor EDA tools and IP? Will the ghosts of past predictions come to pass? Or Will the future be cloaked in purple?
This time of the year is traditionally a time of ghostly tales and predictions for the future. Many pundits have already written their Prophecies for the semiconductor market in 2012. Now it’s my turn.
Perhaps the most infamous rumor in our industry – think of it, as the ghost of seasons past – is the “fab buying an EDA COMPANY” rumor. Most pundits have discounted this speculation over the years, including yours truly. (see, “Are EDA and Semiconductor Markets Cycling Back or Spiraling into the Future?” )
A more provocative ghost is the “CAD buys EDA” rumor. From a systems integration perspective, this idea makes some sense. Yet the lack of overlap between these two market diminishes the business case for any such mergers or acquisitions. (see, “Icahn Seeks Mentor’s Acquisition or Sell-off“)
Others see the specter of a new world order, one that is cloaked in a purple robe that bears the enigmatic symbol SNPS. This ghost of EDA future has been strengthened by the recent acquisition of Magma. Key to this future is that Synopsys has a large portfolio of semiconductor IP (verification).
But IP, while essential, is a tricky element. Most IP has a short profitability window especially in the interface space, e.g., the current version of your favorite standard like USB. This short window must pay for constant re-design and re-validation activities to stay up with the latest standards.
Contrast the short shelve life of most IP – measured in ones of years – with the typical 15 year lifespan of EDA tools. Unless you are well established in a very niche market, like ARM in processors or Denali (now Cadence) in memory, you may have a challenging time in the IP business. Intel had to buy entire companies to improve their IP position in the embedded space.
Synopsys has one other advantage in the IP space thanks to their tool Design Compiler, which can integrate IP directly during synthesis. Conversely, Cadence’s unique position in the IP space is secured through its partnership with the Chipestimate.com portal and the resulting chip design estimation tools. This collaborative site benefits from the expanding IP market without facing the challenges mentioned earlier that face most IP designers and verifiers.
There are other reasons why Synopsys may not be the sole future for the EDA-IP market. Both Mentor and Cadence maintain a strong and growing presence in the embedded board and software spaces – both important sectors that are being integrated with chips. Mentor is especially strong in these related markets. Synopsys might be the leader in the EDA space, but that is a flat growth industry.
So what will the future hold for the EDA-IP world? Consolidation will continue, but real future growth will favor the adaption of successful EDA techniques to new markets, like medical, automotive, consumer and mil-aero. Having the right IP will be the key factor for these new markets. The IP market is also experiencing consolidation, which will lead to the integration of more and more IP. Some have labeled this as the rise of sub-system IP. Others call it the inevitable push toward higher levels of design abstraction.
Whatever you call it, IP – like the future – will continue to unfold in ways the may be predicted yet still hold plenty of surprises!