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Here We Go Again… Portable Test and Stimulus Methodology and Library (PSM)
At this point, you’ve probably heard about the Accellera Portable Test and Stimulus Specification (PSS). You may even have heard a user passionately describe how the PSS revolutionized their flow and how it shortened timelines in a project much like your own. Now your thoughts are racing: “PSS actions with flow objects? Components and exec blocks? Resource declaration and distribution? State machines and configurations? Can these PSS features be applied to my specific needs? Do I need to give up my existing verification assets?”
When Verisity’s coverage-driven methodologies were introduced and a decade later when SystemVerilog (SV) was ratified, we were asked a similar question: “How do I make sense of the native language building blocks?” There is generally a consensus that appropriate answers to such questions involve a methodology, a set of solution patterns, and a generic library.
So here we go again! The Portable Test and Stimulus Methodology and Library (PSM) is a methodology and a library for PSS users, similar to but different from what UVM did for SV users.
The PSS-Compliant Reusable SML Library
In 2011 the Perspec System Verifier introduced a behavior model approach with actions and flow-objects for automating validation tasks. Then in 2013 the Perspec System Methodology Library (SML) was announced, offering a standard set of components, actions, and types to facilitate easy modeling, further automation, and reuse. SML’s productivity and reuse applications are repeatedly proven by user projects and are often referenced in case-studies (by TI, Qualcomm, Samsung, and others).
Consider your recent project’s testbench or design under test (DUT) entity. Depending on your role – HW verification or embedded SW validation – it probably involved masters, CPU cores, or threads that access address-mapped memories. It may have involved sending different kinds of traffic to one or more processing engines and possibly implementing a multi-IP flow in different timing or flows. Much of these needs are handled by SML. SML provides standard types, actions, and functions to enable impromptu or unplanned reuse across projects and teams. The SML layer is generic enough and enables applicability and reuse in all platforms.
A Scenario Example
While this article is not designed for SML training, it shows how to use SML with user-defined actions that should be readable even without any PSS knowledge:
Figure 1. A Scenario Combining SML and User-defined Actions.
This portable scenario starts with a couple randomly-scheduled memory-write actions, followed by a loop of either copy_data or a user-defined DMA transfer, and ends with randomly-scheduled self-checking read_check_data actions. While this seems like a directed test, much of the PSS activity here is randomized. For example, for the masters or threads performing the actions, their execution order (sequential or parallel), buffer sizes, and locations are legally selected considering the available DUT threads, available memories, and other system concerns.
SML provides much of the model component, actions, flow-objects, thread/master pools, memory pool, and more. It provides a simple configuration mechanism to adjust the scenario for your system specification in either PSS code or spreadsheet tables (CSV files).
SML is Key Reuse Enabler
In the scenario above, a PSS tool connects the buffer that is produced by the library write_data action to the user-defined transfer action. The standard memory buffer definition is a key enabler for such reuse, allowing different actions defined by separate teams to be chained into a single integrated scenario without upfront planning.
The provided SML actions (e.g. read_data, write_data and copy_data) constitute a framework for building generic high-level reusable content. Users and vendors can create libraries for such things as coherency, stress, and DVM that are built on top of these memory actions.
Ensuring that SML is a Standard Syntax Compliant Library
There is generally industry consensus about the value of using a standard input format. At DVCON US 2019, Mike Bartley (TVS) presented an article titled “Delivering on the Promises of PSS Whilst Avoiding the Pitfalls on Early Adoption” on this topic and on the hazards of standards’ early days. The article provides multiple suggestions on how to avoid locking yourself into a proprietary solution. One of the guidelines involves using more than a single vendor to check that your code adheres to the PSS Language Reference Manual.
It’s all about the Methodology
PSS actions and flow-objects are powerful features that can be combined in multiple ways to automate different unit-level and system-level verification challenges. While some challenges cannot be codified in generic code, most of the challenges can be mapped into a generic representative modeling patterns. Over the years, we gathered a set of such modeling patterns for many user requests. A few of these examples are complete system models (golden examples) and a few touch upon a specific modeling task (pattern). Beginners and advanced users can benefit from these established practices. The two figures below illustrate examples that are demonstrated and explained as part of the PSM package.
Figure 2: The PSM Simplified System Model with Embedded SW Golden example.
Figure 3: I3C Controller Example Demonstrating HW-Verification Scenarios and Coverage Maximization on top of a UVM Testbench.
Other aspects of the library include packaging recommendations, such as naming conventions, and a directory structure allowing the sharing of reusable PSS packages.
I will cut this blog short as the complete PSM open-code and guidelines are available for download free of charge. If interested, visit http://www.cadence.com/go/PSSMethodology or send an email request to email@example.com.
- Samsung: https://www.cadence.com/content/cadence-www/global/en_US/home/cdnlive/india-2015/proceedings.html
- TI: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/Events/CDNLive/Secured/Proceedings/EU/2016/svg03.pdf
- Qualcomm: https://community.cadence.com/cadence_blogs_8/b/sd/posts/soc-verification-with-portable-stimulus-using-perspec-system-verifier
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