Escalating mobile data consumption, burgeoning artificial intelligence and machine learning (AI/ML) applications, and emerging 5G communications requirements that demand ever-increasing bandwidth are straining the existing cloud data center server, storage, and networking infrastructure. These challenging applications demand high I/O bandwidth and low latency communication.
With hyper-scale data centers requiring network switches delivering bandwidths of 12.8Tbps and beyond, there is strong demand for 112G SerDes IP for the underlying ASICs and SoCs. Cadence’s 112G SerDes technology delivers exceptional long-reach performance with superior margin, optimized power, and area that is ideal for next-generation cloud networking, AI/ML, and 5G wireless applications.
The SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1G to 112G and incorporates industry-leading analog-to-digital converter (ADC), clock-data-recovery (CDR), and digital signal process (DSP) technology that enables the support of greater than 40dB channel. It enables reliable high-speed data transfer over the backplane, direct-attached cable (DAC), chip to chip, and chip-to-module channels for high-performance computing (HPC) SoCs. The Cadence® 112Gbps Multi-Rate PAM-4 SerDes IP in 7nm semiconductor process technology delivers industry-leading power, performance, and area (PPA) ideal for building high-port density networking products for next-generation cloud-scale and telco data centers.
In this video, Wendy Wu, director of product marketing at Cadence, introduces the Cadence 112G Long-Reach SerDes design and COM dependencies.
Market Trends of High-Speed SerDes
56G/112G SerDes IP are high-speed I/Os that support the exponential traffic growth hyperscalar customers are pushing for an 800G standard that uses 8 of 112G links. Industry-leading companies have announced 25.6TB switch products and next-generation 51.2TB is in the cards. These high bandwidth switches use ASICs, with 112G PAM4 SerDes as the foundation IP. Supporting 51.2TB switch throughput requires a high number of I/Os and is difficult to integrate into a single SoC due to package design and power management issues.
In the upcoming co-packaged silicon (CPO) solution, silicon dies and optical chiplets are integrated into the same package, thereby avoiding the long-distance paths over the PCBs, and helping to provide higher throughput. Another application for 112G SerDes is AI/ML SoCs with high-speed I/Os for chip-to-chip connectivity to support multi-socket configuration, high bandwidth, and low latency. 5G applications demand higher bandwidth and 112G SerDes are best suited for this.
112G SerDes technology meets the exploding high-speed connectivity required for emerging data-intensive applications. However, the long-reach connections needed in advanced server and networking equipment are notoriously difficult to design. Due to doubled Nyquist frequency, the channel loss in a 112G system is much greater compared to that in a 56G system, demanding novel approaches to SerDes design as shown in Figure 1.
Due to design impairments in the system, there are challenges in the deployment of 112G SerDes as mentioned in Figure 2. Such design impairments such as SoC packaging, package-to-board impedance mismatch, and crosstalk due to front panel and backplane connector, as well as noise coupling could have a significant impact on the bit error rate (BER) in a production system. These impairments have a much bigger impact as we move towards 112G data rate because of smaller UI and lower SNR.
So, it is important to ascertain that the overall channel performance follows IEEE standards at the design stage. Channel performance should not be judged by insertion loss only. IEEE standards suggest using channel operating margin (COM) for its measurements. By prescribing the minimum value of COM, the standard allows the designers to choose how to optimize the signal impairments and equalization schemes while meeting the BER specifications. The best design should correspond to the maximum value of COM, in the multidimensional design space including RX/TX specifications, crosstalk, jitter, Intersymbol interference (ISI), and noise. The purpose of COM is to characterize a channel in a system with the minimally specified SerDes, but COM can examine the interoperability margin of high-speed serial systems. As per the IEEE 802.3ck specification for 112G, the COM margin must be larger than 3dB.
Cadence 112G SerDes PHY IP
To compensate for the above-said design impairments and challenges which are often inevitable, IP providers provide more margin for their IPs. Cadence 112G Extended Long-Reach (ELR) PHY IP provides additional performance margin to handle design impairments by incorporating reflection cancellation, and enhanced DSP. These enhancements allow us to provide more margin for high loss and reflective channels. The following features are highly effective for the production system:
- A very mature solution based on fourth-generation design and improvements
- Architecture is silicon-proven in Cadence test chip and customer products
- Performance exceeds IEEE specifications
- Programmable reflection cancellation logic effectively mitigates the design impairments, hence reducing production risk, and accelerating time to market
- Built-in intelligence includes firmware-based adaptation, smart power optimizer, and on-die temperature sensor