Semiconductor IP News and Trends Blog
Higher FLASH Throughput for Your Next SoC Design
Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there was no standard to help designers integrate NAND flash components with SoC designs as every vendor has their own set of timings, registers etc. The JEDEC organization came up with Open NAND Flash Interface (ONFI) standard to address this necessity for nonvolatile memory access.
In order to meet the growing demand of higher throughput of many applications, ONFI working group is working a new version of ONFI5.0 in order to improve power consumption and increase throughput. To reach this goal, ONFI TG is introducing various trainings for DQ, DQS as well as differential signals for RE and DQS signal as NVDDR3 or LPDDR4 signaling to capture valid data with smaller data eye in ONFi5.0 specification.
Key Features of ONFi5.0 over ONFi4.0:
- In order to improve I/O Power consumption, ONFI5.0 introduces NV-LPDDR4 Interface operates at VccQ 1.2V
- Mandatory differential low voltage signals to capture valid data eye window and thus achieving higher data transfer frequency from 800MHz to 1200MHz.
- To reduce power/bus noises during high speed data transfer, Optional Data Bus Inversion (DBI Pin) introduced with Encoding for DQ [7:0] bus.
Even though the ONFi 5.0 specification is still under development, we are already seeing semiconductor companies adopting the draft and evolving specification for their next SoC design.
With the availability of the Cadence Verification IP for ONFi5.0, early adopters and JEDEC members can start working with the provisional specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.