Semiconductor IP News and Trends Blog
How AMBA CHI Specification Has Evolved
In my previous article (From AMBA ACE to CHI, Why Move for Coherency?) I talked about how coherency needs have evolved from AMBA ACE to the highly successful and widely adopted CHI architecture.
Since the introduction of CHI, Arm has continually refined the specifications with clarifications, improvements, and new features. Let’s take a quick look at each update and understand why they are important.
2017 (CHI-B) Issue B – first public release
Although there was an earlier Issue A version of the CHI specification a few years prior, which defined the foundation of CHI architecture, it was kept as a non-public release. Update Issue B officially announced in 2017 was Arm’s first public CHI release. Issue B included all the key features (layered functionality, packet-based communication, nodes and unified channels, and credit resource management, etc) introduced by Issue A plus enhancements.
Issue B focused on performance extensions and latency reductions. According to Arm, “These enhancements have been used to improve memory latency and increase data throughput on Arm’s latest generation of IP.” In this release Arm also highlighted, “Cache stashing allows accelerators or IO devices to stash critical data within a CPU cache for low latency access” and “Direct Data Transfer offers significant latency reduction with fast data path return and memory prefetch.”
Other notable addons included:
- Ordering and completion mechanisms which guaranteed the ordering of transactions within a system
- Atomic operations for high performance shared data updates
- Poison and data check fields for corruption and error handling
From CHI Issue B and onwards, the need for legacy ACE FULL has been eliminated. All Arm designs no longer include the deprecated ACE FULL components (though ACE Lite remains in large number of IO coherent devices).
2018 (CHI-C) Issue C – update
Less than a year after Issue B, Arm released another spec update-Issue C. Issue C was not as impactful compared to previous iterations, but it still included new refinement features and spec clarifications.
New features included:
- Quicker ack from requester
- Separate responses from completer
- Combined data and ack.
Though they were not game changers they all aimed to provide greater transmission flexibility and flow.
Issue C also inserted minor clarifications like:
- BE for write transactions
- field changes during retried request
- response during pending snoops
- TraceTag value propagation
2019 (CHI-D) Issue D – update
Issue D gained minor performance enhancements, and like its predecessors, more new features and specification clarifications.
This iteration saw the TxnID width upped from 8 to 10 bits. Why was this minor change important? It increased the number of outstanding transactions allowed. Arm claimed this was, “needed for high latency chip-to-chip interfacing.”
Another key enhancement was the Completer Busy indication.
“The Completer Busy indication is a mechanism for the Completer of a transaction to indicate its current level of activity. This signaling provides additional information to a Requester on how aggressive it can be in generating speculative activity to improve performance.”
Optimizations to the Ordered Write Observation Flow were updated.
“This specification provides a (optimized and non-optimized) mechanism termed Streaming Ordered Writes (OWO) to more efficiently stream such ordered Write transactions.”
Other notable additions included:
- Persist transactions and responses
- Interface parity
- Memory System Performance Resource Partitioning and Monitoring (MPAM)
- ICache Invalidation broadcast signal
With the availability of the Cadence Verification IP for CHI, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.
Want to know more about the next CHI specification update? Stay tuned …