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How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various verticals like Data centers, Cloud computing, Aero-Defense, Mobile, or any other consumer devices. These industries continue to demand higher throughput, energy efficiency, low cost, and above all configurable VIP to match with the shrinking time to market window.

DDR Memory system contains two major components, DDR memory controller (MC) and DDR PHY to access DDR memory. The DDR MC and DDR PHY developments require two different sets of skills, tools, and expertise.

DDR controller needs Digital design expertise, whereas DDR PHY (DFI) needs both Analog and Digital expertise. Thus, DDR MC Design IP companies usually buy an appropriate DFI PHY component from PHY IP companies which eventually need to inter-operate together in the system.

To meet the independent and parallel development, the industry-leading companies came up together to form DDR-PHY org group, which releases DFI specifications from time to time. DDR PHY Org group has released DFI 1.0, 2.0, 3.0, 4.0, 5.0, and 5.1 for DDR and LPDDR memories systems.

Challenges to Verifying the DDR MC, PHY, and Memory Devices

There are many DDR DRAM memory vendors and wide varieties of memory devices to suit various end applications. Each memory device has a large number of timing parameters and configuration registers. Each vendor has its own unique timing parameter values and configuration register values. To come up with the correct timing parameters value for DDR MC, DDR PHY in sync with the selected vendor part number is a huge task and error-prone task.

To overcome the above challenge, the Cadence DFI PHY VIP reads the timing parameters value of the memory device used and sets automatically the DFI timing parameter values for simulation.

The Cadence® Verification IP (VIP) for DFI provides a mature, highly capable compliance verification solution for the DFI protocol. The VIP supports the simulation platform and enables metric-driven verification of IP and system-on-chip (SoC) designs against DFI protocol specifications.

DFI VIP supports both the memory controller (MC) traffic generation and the PHY component, which samples from the DFI interface and drives to the memory interface for different memory variants. The VIP for DFI is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. Cadence Unified DFI Verification IP solution can be configured for DDR4/5, LPDDR4/5, GDDR, and HBM2E/3 to have freedom of choice for SoC designers. Based on configuration selection, VIP will initiate and respond to the command to the interface and specification version.

Key Features of DFI VIP

• Generates constrained-random bus traffic with predefined error injection
• Monitor component contains hundreds of protocol and timing checkers to catch design bugs
• Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
• Integrated with the DRAM Memory Models for complete IP level verification
• MM-DFI Auto Config ​- Automatic updates of timing parameters of DFIMC/DFIPHY VIP based on MM configuration
• Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC

With the availability of the Cadence DFI5.1 VIP, early adopters can start working with the latest specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.

More information on Cadence VIP is available on the Cadence DFI VIP Website.

Chetan Shingala and Salehabibi Shaikh