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How to Verify LPDDR5 from IP to System Level?

LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs and networking systems built for 5G and AI Application. So not only that the JEDEC LPDDR5 specification has seriously increased in its complexity to meet higher bandwidth, better performance and extended latencies, but the whole SoC in which this DRAM resides and the multiple applications that it needs to serve, makes the whole system verification extremely challenging.

Challenges in verifying your LPDDR5 Memory are swapping as your project evolves from IP Level verification during the IP development of your LPDDR5 MC, PHY or device and to Memory sub-system and System level as you start on integrating the memory pieces in the whole SoC.

During the LPDDR5 IP level development your verification scope will need to ensure that your IP is spec compliant to DFI 5.0 for the interface between the MC and PHY as well as LPDDR5 spec compliant deepending on the specific vendor datasheet of the Memory vendor. So depending on the IP component that you are developing, whether your DUT is a PHY, MC or memory device, an appropriate verification environment will need be required based on a few verification components:

• DFI VIP to simulate the DFI PHY or MC components, it needs to check that your DUT is compliant to the DFI 5.0 spec for LPDDR based on your timing requirements.
• LPDDR5 Memory Model to simulate the memory device, it should check that your DUT is compliant to JEDEC LPDDR5 spec and to a single or multiple specific memory vendor datasheets.
• LPDDR5 DFI testsuite to generate all the scenarios needed to ensure that you are covering all the corner cases defined in the specifications.

Once you have fully verified each piece of your memory sub-system you might want to move to an integrated memory environment and ensure that it is still compliant to the DFI and memory vendor specifications.

In this environment, you will be able to reuse the same memory model from your IP level environment while using the LPDDR5 DFI VIP in monitor mode to verify that all training and transactions passing on the DFI interface are compliant to the DFI 5.0 specification and to your specific timing requirements.

Then in your LPDDR5 Memory sub-system and SoC environment your scope is changing as you need to ensure that your LPDDR5 memory can serve all the applications in alignment to your architectural requirements. Regardless if you want to verify your SoC over simulation or emulation, three major tools will be needed:

1. A set of system traffic libraries to generate all the system scenarios to verify

2. A system verification scoreboard to verify the correctness of the data traffic and cache coherency of your system

3. A System performance analyzer tool to identify based on the different generated traffics whether your LPDDR5 memory sub-system is meeting its expected performance goals like bus utilization, maximal latency, minimal bandwidth of each application and the overall system bottlenecks. Such a tool needs to easily connect to the VIPs of your simulation or emulation environment, in order to monitor the data from the relevant interfaces of your SoC and output meaningful performance analysis.

While going through all these challenges from IP level to sub-system and SoC, Cadence offers a wide range of tools which will help you to speed up your verification project while relying on the highest quality and maturity verification tools in the market.

To get more details, please visit Cadence VIP Catalog and Cadence SystemVIP website or simply reach out to discuss with Cadence VIP experts.

In addition, a dedicated Cadence TechTalk session will be given on this topic on September 9th 2021, so for more details please visit Cadence Events website.