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About the Author

Chetan Shingala graduated in Power Electronics Engineering having total 27+ years of experience, with 20+ years for ASIC IP, SoC RTL Design and Verification, FPGA based spec to system design experience with interfaces like I2C, CPU, DMA with Flash and DRAM interfacing devices. Working with Cadence Design System as Software Engineering Director, leading VIP team and Cadence Ahmedabad site since 2016, contributed in growing strength from 30 engineers to 60+ engineers team.