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IP Bring Front and Back Together
Concurrent approaches between IP design and manufacturing appear to be the best way to co-optimize both processes.
Last week, I made time to attended Walter Ng’s afternoon presentation on “IP Ecosystems,” part of the “Design Enablement” track at GTC 2011.
Having spent many years at Chartered Semiconductor, Ng has a strong background in the foundry part of the chip business. I was curious how hear who he would combine the typical front-end design activity of IP creation with the back-end manufacturing process. My first challenge was one of definitions. What exactly was “design enablement?” It seems to refer to the SoC development activity that spans the design through manufacturing life cycle, including both technologies and processes from the EDA, IP, library, DFM and design services segments. Back in 2009, Globalfoundries hired Curtis “Mojy” Chian as senior vice president of design enablement. Doug Grose, then CEO of Globalfoundries, explained that design enablement would be one of the most critical functions to support the acquisition of new customers as the company continued to transform from a foundry.
Earlier in the day at GTC2011, Chain talked about the importance of collaboration for future designs. Throughout his presentation, design IP was closely tied with the downstream manufacturing process. Where traditional offerings would have used component IP, future solutions would require “silicon-verified, platform-based design IP.” Complex designs mandated a design reuse methodology for which IP plays a lead role. But semiconductor IP must be tightly coordinated with manufacturing sensitive design approaches, such as DFM and yield optimization.
This understanding brings me back to Ng’s presentation, which dove into the details of IP co-optimization. I wouldn’t elaborate further, since Ng has already described this approach in detail in a recent Chipestimate newsletter: “Concurrent Collaboration Ensures Optimized IP Development at the Leading Edge”
It is sufficient for my discussion to note that today’s leading edge IP development must be closely coordinated with the manufacturing process. Small nodes and increasingly complex design rules mean that designers must have a deeper appreciation of the manufacturing process to optimize their IP designs.
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