Semiconductor IP News and Trends Blog
Follow our semiconductor IP Insider blog section for up to date information on the latest technological advances in silicon IP
May 13, 2022 - By Sangeeta Soni
If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL … Continue reading
April 29, 2022 - By Dimitry Pavlovsky
As discussed in the last installment of the blog, a robust system level scoreboard is essential for functional verification and performance validation of modern SoCs. A properly architected system scoreboard should work in conjunction with interface Verification IPs (VIPs) and … Continue reading
April 22, 2022 - By Yeshavanth B N
In ARM MMU-based systems, DTI protocol defines a standard way to communicate with Translation Control Unit (TCU). DTI protocol is a point-to-point protocol with each channel defining a link. The communication with TCU will be from two different components, and … Continue reading
April 12, 2022 - By Shyam Sharma
As the device frequencies and the data rates go up with every new generation of Interface and memory devices, sampling of the signals and the transferring of the data b/w Initiator and target is being increasingly difficult with ever shrinking … Continue reading
March 29, 2022 - By Salehabibi Shaikh
DDR Memory is an important part of a wide array of electronic system designs in various verticals like Data centers, Cloud computing, Aero-Defense, Mobile, or any other consumer devices. These industries continue to demand higher throughput, energy efficiency, low cost, … Continue reading
March 17, 2022 - By Krunal Patel
Cloud computing, IoT (Internet of Things), machine learning, big data, and data centers are a few of those buzzwords levitating around digital transformation in recent years and we are quite familiar with these terms. These technologies have much of a … Continue reading
February 18, 2022 - By Neelabh Singh
The objective of USB4 protocol to achieve high speed signal transmission and thereby providing high data bandwidths for protocol tunneling would not have been possible without USB4 re-timer. Like several other serial protocols where the generation-by-generation higher link speeds are … Continue reading
January 24, 2022 - By Min Lei
In my previous article (From AMBA ACE to CHI, Why Move for Coherency?) I talked about how coherency needs have evolved from AMBA ACE to the highly successful and widely adopted CHI architecture. Since the introduction of CHI, Arm has … Continue reading
December 23, 2021 - By Jon Jacobsen
Interview with the CEO at Silex Insight – Michel Van Maercke Recently, the news landed in your mailbox that Silex Insight has sold its video division to Australian expert Audinate. We sat down and talked with Silex Insight’s CEO Michel … Continue reading
December 10, 2021 - By Krunal Patel
The emerging 5G network is the 5th generation of the cellular network. A 5G network allows handling a thousand times more traffic than today’s networks. Not only is it faster than the 4G network, but it also has lower latency, faster … Continue reading
November 9, 2021 - By Bipul Talukdar
A well-repeated truism throughout the semiconductor industry is that chip design verification is complex and often takes up the largest portion of a design project’s schedule –– sometimes as much as 70% –– and an ongoing challenge facing verification engineers. … Continue reading
October 28, 2021 - By Krunal Patel
At a particular point in time, the automotive industry continued to add more and more sensors and electronic control units to vehicles. All these sensors and actuators used to connect through CAN and LIN buses. However, since the introduction of … Continue reading
October 11, 2021 - By Shyam Sharma
Even with the DRAM capacity going up with each generation of DRAM, the demand for memory densities by variety of applications, is growing at even faster rate. To support these high memory densities and bus width requirements (that are typically … Continue reading
September 22, 2021 - By Sangeeta Soni
The concept of Trusted Execution Environments (TEE) was developed in the early 2000s to standardize key encryptions, end-to-end security and authenticity, and confidentiality of devices in a system. With the increase in computing and connected devices due to IoT, there … Continue reading
August 20, 2021 - By Thomas Wong
DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint event this year. Cadence had an opportunity to present at a session on behalf of PCI-SIG. The topic of the presentation is “PCI Express Technology: Accelerating Automotive Connectivity, … Continue reading
August 9, 2021 - By Sriram Sharma Kalluri
Embedded Security Using Cryptography In the previous blog post, “Securing Offload Engines for a Robust Secure SoC System,” we briefly looked at some of the methods employed for achieving embedded security, i.e., cryptography, hardware partitioning and isolation, and hardware root … Continue reading
July 20, 2021 - By Dimitry Pavlovsky
Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of data servers and high-performance mobile devices. Being … Continue reading
July 19, 2021 - By Claire Ying
The new cloud, AI, Analytics, and Edge usage models with exponential data growth and connection drive the evolution of high-bandwidth PCIe (Peripheral Component Interconnect Express) version 5.0 and 6.0, CXL (Computer Express Link) version 2.0 and 3.0. Every component can … Continue reading
July 1, 2021 - By Sriram Sharma Kalluri
Protecting offload engines requires both software and hardware solutions. Welcome to the Securing Offload Engines blog series where we will explore different approaches to security implementations and look at system examples involving Cadence Tensilica Xtensa Processors. In this blog, we … Continue reading
June 1, 2021 - By Dimitry Pavlovsky
As discussed in the previous blog, the AMBA® 5 specification updates introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA® 5 CHI (Coherent Hub Interface) specification. Among them is a new class of atomic transactions which … Continue reading
November 12, 2020 - By Roddy Urquhart
The area of any part of a design contributes both to the silicon cost and to the power consumption. A simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. A processor is never in isolation but … Continue reading
October 14, 2020 - By Dr. Evans Yang
Artificial intelligence will play a pivotal role in the future of information security. By combining big data, deep learning, and machine learning, AI give machines life; they can imitate human learning, replicate work behaviors, and bring new ways to operate … Continue reading
