PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations.  Aligned with this, Synopsys also announced the collaboration of  its Design and Verification Solutions with  Astera … Continue reading »

The Design and Verification Conference and Exhibition (DVCon U.S.) held earlier this year once again brought chip developers together with EDA tool vendors to tackle major issues. Continue reading »

There are two famous parties in the EDA world. The Denali Party by Cadence, of course. I’m afraid you missed that one for this year—it is always on the Tuesday of DAC. The second one is the HOT Party organized by … Continue reading »