Semiconductor IP News and Trends Blog
IP Core Interconnect leads to MARC at IDF2011
My quest for news about the illusive Intel On-Chip System Fabric (IOSF) at this year’s Intel Developers Forum (IDF) reveals clues about other core interconnect technologies.
I almost felt like adventurer Indiana Jones looking for a fabled, all connecting wonder of the silicon world. But instead of a steaming jungle, I was inside an air-conditioned exhibition hall at the IDF show. My goal was to learn whatever I could about Intel’s new System-on-Chip interconnect technology known as IOSF.
My first stop on this quest was the “Many Core Application Research Community (MARC)” booth in the Intel Lab’s section of the hall. Divya Kolar, Technical Marketing Engineer and Mike (last name unknown), were hosts at the booth. Both were software engineers degreed in computer science.
Since my questions focused on hardware rather than software, I learned little about Intel’s new on-chip interconnect fabric. But I did learn something about Intel’s other interconnect strategies.
MARC grew out of research on “many-core” processor research, originally envisioned by the Tera-scale Computing Research Program. One recent result has been a 48-core Single-chip Cloud Computer. This research endeavor is now known as the MARC, a program where the academic and industry researchers submit proposals to run on the many-core platform for next-generation software research. Using the many-core technology, community members will have another tool to examine challenges in parallel programming applications.
I call it selective crowd-sourcing.
Unfortunately, I learned little about the actual interconnect technology between the 48 Pentium cores on a single-die many-core chip. Divya did share that an open standard “Message Parsing Interface” (MPI) was used to communicate between the processor cores. When I asked how this interconnection related to the newly announced Intel On-Chip System Fabric (IOSF), neither host knew or was telling.
Mike did acknowledge that interconnections were one of the most significant issues for both for on-chip and off-chip interfaces. “As you put multiple dies together that have multiple processors inside them, you run into system interconnect challenge. Then, as … you connect multiple computers together, you’ve got another level of interconnect challenges.”
He further explained that all of these various-levels of interconnection had become an important issue in the “millions of processor” program. In this activity, Intel has been working US government on a project called the, Ubiquitous High-Performance Computing (UHPC).
As I was ready to leave, somewhat dejected that I had learned nothing about ISOF, both Mike and Divya reminded me that the MARC community was but one way in which Intel is exploring the on-chip interconnect challenge. One benefit of working at the world’s largest semiconductor IDM was that the company could experiment with multiple paths and directions to solve the issues. Indeed, that was a major part of the role of Intel labs, i.e., to evaluate many different technology directions.
As I was leaving, Mike suggested that I seek out “MIC.” My comical expressions led him to explain that MIC referred to the Many Integrated Cores project. MIC was more about hardware direction and architectures, while MARC focused on parallel software development.
I grabbed my Intel backpack, thanked my hosts, and headed out to find MIC.
Footnote: Further research has revealed that the MARC architecture does not support cache coherency. This relates to an earlier blog on ARM’s recent announcement on the same subject. (see, “Cache Coherency IP Catches at DAC” ) I’ll return to this topic in a future blog.