Semiconductor IP News and Trends Blog
IP Subsystem – Milestone or Flashback
By John Blyler
Traditional responses to increased SoC complexity, such as greater aggregation, tighter integration and more comprehensive verification, now face new inflections in the changing world of semiconductor IP development. Such challenges present fresh opportunities to both engineers and the bloggers who cover them.
Semiconductor IP technology is at a milestone. It is changing in a fundamental way. The milestone was highlighted late last year by Rich Wawrzyniak of Semico Research in a report titled: IP Subsystems – The Next IP Market Paradigm. “It doesn’t make sense that the forces of integration only apply to silicon. It’s going to apply to IP,” Rich explained. He was right. (See Semico Research’s latest blog)
The report predicted that third party semiconductor IP (SIP) would grow from 15.2% to reach $2.7B by 2011. One might conjecture that the rise in IP reflected a rise in design starts. Or it might mean that more derivative designs are being included in IP numbers. Regardless, this increase in IP is interesting in light of the emergence of the first IP Subsystem products from major IP vendors. Semico expects these products to produce a huge 85.4% growth rate. While this number is impressive, it does reflect the relatively small base from which this new product grouping will start.
What is driving the emergence of IP subsystems? The litany of causes is so common that one can almost chant them: increased complexity, shrinking time to market and cost constraints. Each of this causal trinity supports the aggregation of IP in both ASIC, ASSP and FPGA implementation.
More and more functionality – feature sets, if you like – are being integrated onto a single chip. The complexity of verifying and connecting so many individual collections of IP, often from multiple vendors, can greatly increase the risk of a mistake or flaw. Integrating and verifying collections of IP into a subsystem block would reduce this risk.
One might argue that industry standards interfaces will reduce the risk of incompatibility among separate IP blocks. This is true in that the risks are lessened. But standard interfaces can have slight differences in interpretation and compliance verification testing. Further, evolving standards, such as those in emergent markets like wireless communication, are difficult to nail down. All of which add to the challenges of integrating disparate IP blocks.
Closely related to technical complexity obstacles is the shrinking design time window. Meeting the time-to-market demands necessitates the co-design, co-verification and tighter integration of both hardware and software (drivers, RTOS, middleware and sometimes application) subsystems within a SoC. The use of pre-verified fully integrated IP systems will reduce the risk of missing key market windows. One should note that in this usage, IP applies to both semiconductor hardware and embedded software subsystems
Globalization and the rise of consumer markets have creased the profitability margins for new products. Increased cost in the form of decreased revenues results from missed time-to-market windows. Mistakes and errors caused by complexity result in increased development costs, typically in the later verification and integration (pre-product) phases of the life cycle.
These challenges in IP aggregation, which are essential for SoC designs, should come as a surprise to no one. Equally non-surprising are the examples of IP subsystems. Consider a simple subsystem comprised of a processor core, USB full- or hi-speed device controller core, and related Internet software stack. Another example would be an end-to-end memory IP subsystem that integrates DDR memory controllers and memory schedules with all the Amba bus and verification IP in-between.
I agree with Kurt Shuler from Arteris and others who note that, IP Subsystems are Nothing New. The concept of integrated and verified subsystems is a flashback to the earlier days of silicon integration. Further, it is the tried-and-true systems engineering method for dealing with complexity, tight schedules and narrowing costs. But applying this approach to the semiconductor IP market with all of it intricacies in the EDA tool flow, global security, cloud computing and semiconductor manufacturing markets is something new. And that is a topic worth covering.