Semiconductor IP News and Trends Blog
IP Tagging Gains Renewed Interest
Hard and Soft IP tagging, originally started by the now defunct VSI Alliance, is gaining renewed interest as the semiconductor and EDA markets depend more and more upon design reuse.
Yesterday, I read an interesting blog about IP tagging; “IP Tagging Resurfaces.” What caught my attention, aside from a general interest in semiconductor intellectual property (IP), was the comments by Kathy Werner, IP strategy and business manager inside of Freescale’s Design Technology Organization. Many of you might remember Kathy as the past president of the Virtual Socket Interface Alliance (VSI Alliance).
Before sharing Kathy’s insights on IP tagging, I need to provide a small bit of historical context.
The VSI Alliance was formed in 1996, during the very early years of IP reuse. It was a leading IP standards body until the summer of 2007, when budget cuts and competition from other organizations – namely Spirit and Si2 – resulted in closure of the alliance. Eventually, the key VSI Alliance standars were donated to the IEEE and Accellera organizations. (Spirit has since been merged into Accellera.)
Two key standards that emerged from the VSI Alliance were Quality IP (QIP) and Soft and Hard IP Tagging. The QIP Metric, which has been downloaded by hundreds of companies worldwide, provides an accepted measure for users to judge the mature of an IP block. For example, much of the IP found on Chipestimate.com contains a Quality IP rating.
The second key standard deals with IP tagging, a subject that has recently resurfaced in the news. Tagging is a mechanism that defines the ownership and origin of IP. From the Accellera site: “This standard provides a way to track both hard IP and non-hardened or soft IP information throughout the design and development process. The design process can include editing, synthesis, timing, placement, wiring, and other steps leading to GDS II generation. … At each level, tracking information is obtained from the previous level, and is transported to the next level using the appropriate output format.”
The hard IP tagging standard has found wide use. One of the early adopters was TSMC. Hard IP tagging consists of a text string included in the text layer of a GDS. Any tool that can read GDS can read the tag to determine the origin and owner of the IP. This is an important way to insure the quality and, to a lesser degree, the security of the IP block.
Soft IP tagging remains more problematic. As noted by Accellera; “Control of third party IP source is lost once IP is licensed, unlocked or otherwise made available in clear code.” This is why Accellera is currently seeking help from the community for tagging of soft IP; “Accellera Announces IP Tagging Effort, Calls for Participation”
Hard IP is easier to tag as it moves through the design flow. For example, RTL code is synthesized on a particular date by a particular company’s tool, explained Kathy Werner in her interview with Ed Sperling, Editor-in-Chief of the System-Level Design .
But soft IP presents other challenges for tagging, in part because soft macros are meant to be customized and modified by the end user before they are finally laid-out. If one tool in the development chain didn’t generate or include an IP tag – which is often the case with soft IP – then the benefits of tagging are lost, Werner explains.
It is satisfying to see that several of the initiatives – like IP tagging – started by the original IP standards body back in the mid-90’s have gained even more relevance in today’s growing market for design reuse.