Semiconductor IP News and Trends Blog

Integration Issues Await Emerging IP Tools?

Will recently introduced chip design front-end tools “play” well with existing IP tool suites? Adam Traidman shares his thoughts.

The recent rise of semiconductor intellectual property (IP) front-end modeling tools is a good sign for the System-on-Chip design and manufacturing market. But it may be a mixed blessing. As any user of EDA applications will tell you, more tools may be a help or a hindrance depending upon how nicely the tools “play” together.”

Are there integration issues between the new and existing IP tools? To shed light on this question, I sought out Adam Traidman, General Manager of Chip Planning Solutions at Cadence. Prior to joining Cadence, Traidman was the CEO and president of Chipestime.com. What better person to explain how existing IP estimation tools fit or conflict with the recent front-end design tools offered by Carbon and Synopsys? In our email exchange, Adam also hinted at new subsystem capabilities under consideration.

Blyler: How do the recent front-end modeling-tool offerings compare or fit with your estimation tools? Let’s start by comparing the Synopsys TLMCentral.com site.

Traidman: Synopsys management and I have discussed this in detail, and we both agree that the sites are complementary and represent a unique value to our mutual customers. TLM Central is a central forum for information and downloads of TLM views for various IP. ChipEstimate.com is a central database for all design and verification IP, which may or may not include IP with TLM views. Because we don’t focus on TLM IP or offer any downloads of TLM models, the sites are largely complementary. With regards to our chip-estimation tool, we use physical IP views (think gate counts and black-box sizes for soft and hard IP, respectively). So TLM really doesn’t factor into the IC estimation arena at this time. I guess it’s more relevant to consider that TLM IP really just means TLM views of various design IP. Thus, the IP isn’t specific to one portal or the other. The Synopsys site just aggregates IP with the TLM views available and information on how designers can leverage TLM to improve design efficiency.

Blyler: How does Carbon’s IP Exchange compare to the Chipestimate.com approach?

Traidman: The Carbon site appears to be along the lines of Synopsys’ site—meaning a complementary offering that highlights the system-level views largely used for verification/simulation.

Blyler: These tool comparisons might be easier if Chipestimate.com offered an application template from which users could select an entire subsystem block for evaluation (e.g., to design a multimedia IP subsystem or even a simple mobile phone). Is this an upcoming possibility?

Traidman: That’s a fantastic enhancement idea and one that we’ve heard consistently from our customers for some time. Technically, this is possible today in InCyte Chip Estimator and Cadence Chip Planning System (CCPS), but one must drop the entire “subsystem” as an IP into the design. Because we are agnostic to the level of abstraction of any component (e.g., you can drop in an ADC or entire graphics subsystem with analog/digital portions), it’s possible. But the idea of grouping together atomic IPs across hard IP, soft IP, memories, and I/Os—maybe even with nuances like library and Vt dependencies—is something we’re working on implementing now and is in our committed roadmap for both products.