Every new generation of process advancement, and the new transistor structures that come along with those advancements, offer the promise of better performance, lower power, and reduced area. This is the trend predicted by Moore’s Law. The emergence of FD-SOI, (Fully Depleted - Silicon on Insulator) and its subsequent maturity over the years, has made it one of the seminal process advancements for low power semiconductor design. Although not as prevalent as the mainstream bulk CMOS process, FD-SOI has provided an important set of benefits to semiconductor product designers. These advances intersect with market demands for devices with more intelligence and better connectivity. Envisioning and developing these new products require the support of an entire ecosystem. An ecosystem where an IP vendor, like Mixel, and a semiconductor company, like (NXP), can partner and contribute their skills so that the benefits of technology advances become a reality. This does not just happen. It is important to appreciate the investment necessary to build an ecosystem to support a process like FD-SOI. Although the choice of foundry, process technology, or silicon IP is not a concern of the consumer using such devices, it is of critical concern to those of us who need to build these products.
What differentiates FD-SOI as an important process technology? There are a set of intrinsic benefits. There are also specific operational optimizations that improve both the power and performance of FD-SOI devices. In this article we detail those benefits in comparison to bulk silicon, and examine how this translates to improved power, performance, and area metrics.
Figure 1 shows the two transistor architectures, Bulk CMOS versus FD-SOI. Compared to Bulk CMOS, FD-SOI introduces an ultra-thin buried oxide layer and a thin channel, which provides better performance and enhances ultra-low power (ULP) operation. Notice the FD-SOI device is built above a buried oxide layer. It has a raised source and drain and very thin uniform channel under the gate. As a result, the transistor performance is more predictable. FD-SOI transistors have less performance degrading parasitics and other short channel effects seen in Bulk CMOS architectures. Note that in Bulk CMOS the drain and source are doped directly into the substrate silicon along with the channel implant. This structure produces parasitic capacitances between the source and drain and the substrate. This transistor architecture also creates what is called Gate-Induced Drain Leakage current and causes variability in Threshold Voltage (VT). The additional effect of Drain-Induced Barrier Lowering (DIBL) makes it exceedingly difficult to completely turn off the device under high drain voltage conditions. FD-SOI architectures drastically reduce these parasitics and operational deficiencies. In FD-SOI, the buried layer oxide shields the source and drain, drastically reducing the GIDL parasitics. DIBL is reduced by using an ultra-thin channel. The shallow channel improves the gates ability to completely turn-off the transistor. The fact that the channel is fully depleted reduces the leakage and reduces VT variability. Overall FD-SOI devices significantly reduce gate capacitance and the parasitic capacitances seen in Bulk CMOS. This improves key performance metrics for analog design, namely lowering dynamic power (and peak power), improving transconductance and fT.
In the past, the hierarchy of importance for SoC’s was “Performance, Power, and Area” (so coined PPA). Now, as Mobile, IoT, and Edge-based applications take center stage in the market, Power and Area have moved ahead of Performance. This means for a given low power and area target, you tune for performance. FD-SOI excels as a low power foundry process for wearables and other battery powered applications. When choosing silicon IP, “power” and “area” are now critical parts of a decision matrix. Reducing average power, peak power, and especially leakage power is critical in today’s silicon applications. A combination of all three is important, as concentrating on one does not specifically guarantee improvements in the other two. Peak power is a gating issue in package choice, a key factor in the total cost of a chipset, and the overall Bill of Material (BOM) of a finished product. The success of a battery powered devices often hinges on its ability to have a long and predictable lifetime operation. Since many of these devices are in standby mode most of the time, reducing leakage power is a major design goal. Minimizing the total power profile will not only extend the battery life but it may reduce the package cost by lowering the thermal requirement. Total power is a function of dynamic power (or switching activity), short circuit current, and leakage power. Dynamic and leakage power are a focus and become key design objectives in building a low power device. They are calculated using these formulas:
The FD-SOI transistor has less dynamic power consumption because of the lower effective capacitance (CTOT). In addition, as shown in Figure 2, the Subthreshold Slope (S) is steeper, and the transistor turns on faster (into overdrive), reducing the threshold voltage (VT). For a lower supply voltage (VDD), you get the same performance. You can design using a lower VDD. So, when the device is active, the combination of lower total capacitance and the use of a lower supply voltage reduce the overall dynamic power, as compared to Bulk CMOS. FD-SOI transistors also typically have a lower IOFF current than Bulk CMOS. The other key power metric is leakage power. When a transistor using Bulk CMOS is operating in standby mode or “off”, current still flows and drains battery charge. The fully depleted thin channel in FD-SOI lowers this subthreshold leakage current. When an FD-SOI device is turned off, it’s off, as compared to the leaky Bulk CMOS device. In addition, FD-SOI allows for the use of Body-biasing. Body-biasing in reverse mode can reduce leakage up to 50X. This is a key differentiating feature since most IoT and wearable devices spend most of their time operating in stand-by mode.
Figure 3 shows the Body-biasing architecture for Reverse and Forward biasing the substrate. As the Reverse Bias (RBB) is increased, the subthreshold leakage current drops proportionally.
More reverse bias means less current. This is a significant advantage in IoT and wearable devices applications that operate on battery power. Interestingly, Forward Biasing (FBB) the substrate increases the performance. Putting increasing FBB voltages on the substrate lowers the threshold (VT) and results in higher gate overdrive ((VDD-VT) – as shown in Figure 2). Adjusting FBB can dramatically boost performance while the device operates at an optimal power level. Performance boosts of more than 60% using a 1V supply have been seen. So, using Body-bias control and applying it in RBB or FBB means the power and performance operation of the device can be tuned for the workload and operating conditions of the application.
In a recent power analysis experiment, Mixel achieved a power savings of 50% for the Fast-Fast (FF) process corner. For the typical corner (TT), in the same experiment, a 14% power reduction was achieved while reducing the total active area (W/L of transistors) by 55%. Such area and power savings are a persuasive incentive to use FD-SOI.
It’s also worth noting that Body-bias can be used to compensate for die-to-die process variation. Research has indicated that when no bias is used some parts failed to meet their required speed, especially in the Slow-Slow (SS) process corner. FBB can be used to boost the speed of those parts, recovering them for use and increasing the overall yield. Alternatively, RBB can be applied to FF parts to reduce leakage current.
Better Analog Design
Although low power design is such an important design objective these days FD-SOI does offer some general benefits for analog and mixed-signal design. These include:
- Better Gain (gm/ID)
- Higher Bandwidth (ft and fmax)
- Improved Matching (A2VT/2WL)
Depending on the type of analog and mixed-signal IP under development, one or more of these benefits adds to why FD-SOI is a better foundry choice for building mixed-signal silicon IP versus Bulk CMOS. The scaling benefits for Bulk CMOS have been slowing over the last 10 years. Even before the recent stress to Moore’s Law the scaling benefits for digital are often better than those for analog. New geometries often introduce parasitics and process variations that make it more difficult for analog designers. This is particularly true for Bulk CMOS and are often grouped together as SCE-Short Channel Effects. Since today’s SoC designs are mostly digital, it is up to analog designers and analog IP providers to make their designs in the process that makes the most sense for the “digital” customer. Bulk CMOS is the dominant process today and it has historically been the low-cost manufacturing option. But now, moving below 28nm, down to 16nm/14nm FinFET architectures, it’s not just a technical challenge, but an economic one as well. This move can be simply too expensive for products with shorter life cycles and smaller volumes. Furthermore, the emergence of the IoT market is opening a set of large unit vertical markets – consumer, industrial, medical, smart homes, and wearables, all of which can benefit from the analog design advantages of FD-SOI. Products for the new generation of IoT require a proper mix of time-to-market, low power, on-chip flash memory, interconnect IO, and RF/analog. FD-SOI provides the right mix to achieve better performance, with lower power, at lower cost—without the need to move to the more costly FinFET process.
If we look in more detail at some of the Figures of Merit (FOM) that FD-SOI provides the designer, we can further see the benefits of FD-SOI. gm (transconductance) is one of the more important key device metrics, or FOM in analog design. It plays an important role in amplification, an essential characteristic in many analog functions. It is essentially a measure of output current over input voltage. It is important as an indicator of current drive based on input voltage in an individual transistor. Gm/ID is the transconductance efficiency (at a particular drain current). As shown in Figure 4, FD-SOI at 28 nm has a greater transconductance efficiency per gate length compared to 28nm Bulk CMOS. That increase provides better transition efficiency
for a given ID and transistor area (W/L). Not only does 28nm FD-SOI provide better gm based on typical scaling (moving from 40nm to 28nm), but it provides better intrinsic or “self” gain (gm*R0) due to its thin channel, lower gate capacitance (lower Cox), and the reduction of other SCE (Short Channel Effects). Further improvement comes from the analog design technique of using current mirror topologies with higher output impedance so that there is less degradation of the output resistance (R0); so, you approach the maximum gain of the device achievable in the process. FD-SOI is better for analog applications where transconductance, or more efficient amplification, is a key design objective. Note that for an individual transistor Length (L), analog transistors have larger Widths (W) to achieve a higher gm. Analog designs in Bulk CMOS typically avoid the smallest transistor lengths because the self-gain reduces with smaller process geometries (i.e. more SCE). FD-SOI mitigates this degradation and provides the same performance in a smaller area (W·L).
Two other FOM important in analog design are ft and fmax. These parameters provide a measure of current gain and power gain respectively, as a function of frequency. ft is the frequency at which the current gain is unity (or 0 dB).
We can look at a simplified view of ft (equation above) as being proportional to the transconductance over the gate capacitance and approximately proportional to the inverse of transistor Length square (L²). In small signal amplification, as the input frequency increases, vgs decreases, reducing the output current iD given by gm*vgs/CTOT, ignoring for now the resistances. This shows that the current gain of the transistor is not fixed but is a function of the frequency. Because FD-SOI has a lower total device capacitance (CTOT) and a higher the gm, the ft (unity gain) is higher, expanding the useful amplification range (Gain-Bandwidth). This device metric is better in FD-SOI than for Bulk CMOS.
fmax is where frequency at which the power gain is unity (0db). It is also considered the maximum frequency of oscillation. fmax is considered a better FOM than ft because it considers the SCE parasitics in Bulk CMOS. Looking at a simplified relationship between fmax and ft there is the following:
In an FD-SOI process, the power gain and maximum oscillating frequency of the transistors are better due to higher ft. ft / fmax in 28nm FD-SOI is comparable to a 16/14nm, lowering Vtgm even more, as does lowering the total capacitance (gate and source/drain). Overall, the increase in current and power gain increases the maximum data rate, allowing FD-SOI to support higher performing analog IP (like high-speed SERDES).
The top of Figure 5 illustrates the variation of ft and fmax as a function of vgs. Below that is shown the lower capacitance per gate length at 28nm, further illustrating the advantages of FD-SOI for these analog design metrics.
Another concern of analog designers, one that is key to achieving high performance and high precision, is the circuit layout. Poor transistor layout choices lead to mismatch that negatively impacts circuit performance. Transistor architectures, as defined by the process, and the Width and Length dimensions of those transistors, introduce variability into the design. For Bulk CMOS, random dopant fluctuation (RDF) due to SCE and halo doping introduces significant device variation that degrades performance and reduces yield. The FD-SOI process reduces the device variability because the channel is thin and undoped. The typical method of reducing variability in Bulk CMOS is to increase the W/L of your transistors to increase gate overdrive.
Designing in FD-SOI changes that paradigm. Devices with the same transistor area (W·L) deliver the same or better performance for the per given unit area. This was illustrated in Figure 1 earlier. Figure 6 shows the overall area and variability reduction that is achieved in an FD-SOI process based on research at IBM. FD-SOI designs not only have better mismatch characteristics, but they are also more area efficient.