FD-SOI in action with NXP’s i.MX 7ULP
The benefits of FD-SOI extend well beyond the advantages outlined for analog and mixed-signal design so far. It is a great technology to build products with extreme low power requirements. SoC platform products for low power and lower cost IoT devices and wearables are in high demand. The IoT segment alone is expected to grow to $75 Billion by 2025. To meet this market demand, NXP has introduced the i.MX 7ULP platform and family of SoCs.
These portable battery powered devices need to operate at the lowest possible active and standby power with as small of a die as possible. Being able to operate at a lower voltage not only reduces power but improves the battery life of these devices. This was achieved through a combination of process selection and design architecture.
The FD-SOI process itself provides an optimized solution which not only improves performance and keeps power consumption down but does so with minimal die area. The i.MX platform was built on the same Samsung FD-SOI process which enables tuning silicon for lower power or performance.
Figure 8 is a block diagram of the general platform architecture of the i.MX 7 ULP platform. The platform supports several different product variants. As aforementioned, NXP used many of the differentiating features of FD-SOI to tune the power-performance benefits to optimize their silicon. Some of these included:
- Improved electrostatics enabling the use of shorter gate lengths
- Reduced device parasitics to improve performance
- Device Back-bias allowing for lower VDD while maintaining performance
- Device Back-bias for drastically reducing stand-by power
- Device tuning with Back-biasing to compensate for process variation
The i.MX platform features flexible connectivity options and ultra-low power operation in active and standby modes. The heterogeneous domain computing architecture (Cortex A and Cortex M) allows for discrete partitioning of power domains so most of the chip can be turned off leaving the Cortex M operating at exceptionally low power for those always on requirements.
NXP also optimized their design to improve power efficiency. With heterogeneous domain computing architecture, NXP was able to power gate as much silicon as possible for the least amount of leakage. There were multiple lower power modes implemented like run low-power, stand-by or deep state modes. Each of these low power modes were optimized to maximize power efficiency.
NXP worked closely with Mixel on understanding markets’ demands to deliver the right mix of features and power capabilities within the FD-SOI process technology. IP selection like Mixel’s power efficient MIPI DSI TX IP was very crucial for further improving power efficiency.
By combining the right process, design architecture, and IP, NXP was able to reduce the power consumption dramatically. The results speak for themselves. In Figure 10, the stand-by power savings for the i.MX7ULP were 5-20 times less than previous generations of NXP processors with a 2-6 times reduction in runtime power.
NXP provides a complete evaluation kit (EVK) so customers can quickly prototype their product concepts. The NXP i.MX 7ULP evaluation kit offers 2D and 3D graphics options as well as Wi-Fi and Bluetooth wireless solutions.
Mixel’s IP in the FD-SOI Ecosystem
To leverage the benefits of any new technology a complete supply-chain ecosystem must develop. In the case of FD-SOI, this involves the foundry, silicon IP developers, EDA companies, packaging, and production testing companies. These ecosystem players all provide key services to the semiconductor product developer. The foundry is the factory. Silicon IP developers provide key elements included in the end chip manufactured in the foundry. EDA companies provide design tools used to perfect the designs for manufacture. Packaging and test services are finishing stages necessary for efficient and reliable product chip development. The actual process development and the silicon IP are the primary investments in bringing up a new foundry process technology (FD-SOI). Semiconductor companies must see some return-on-investment to develop a product on a new process technology. But to realize that value they also need access to key silicon IP on that technology. Without IP there will be just too much cost and time delay completing a full chip design.
Foundries monetize their investment based on wafer sales. Silicon IP companies monetize their investment based on unit IP sales and some also charge royalties. Both the foundry and IP provider spend real resources and money bringing up a new technology. Silicon IP suppliers sell key design elements (IP blocks). This has been the trend for more than 20 years now. IP companies leverage their special knowledge, whether in processor architectures, protocol, interface, or memory design to produce IP blocks that can be easily integrated into a full chip product design. In the case of Mixel, this special expertise includes detailed knowledge of how to design and implement MIPI IP, LVDS IP and other types of interface blocks.
Table 1 shows the list of Mixel IP available on FD-SOI process nodes for 28nm FD-SOI and 22nm FDX. Mixel’s expertise in mixed-signal and analog design, and their deep understanding of the process, are significant factors in the success of their development. It is measurable in robust operation across a wide range of operating conditions.
Summary
FD-SOI at 28nm and 22nm continue to offer design and performance benefits for those developing the next generation of IoT and Mobile semiconductors. The mix of analog and digital improvements and the ability to optimize the power utilization based upon the application make FD-SOI a great choice for product design. A substantial ecosystem has developed providing essential silicon IP, design, package, and test support, making it easier to produce timely products at cost that provide enough margin and reasonable return-on-investment. Taking this all together, FD-SOI deserves another look. Delivering on low power, small form factor, and better performance is the promise of all new foundry technologies. FD-SOI delivers on all three.
Read Part One - Is it time to look at FD-SOI -- Again? Part 1: A technical perspective
