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Key Hardware IP Enables the Software-Defined Vehicle
Tim Messegee
Rambus |
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The evolution of automobiles to software-defined vehicles has entailed the deployment of semiconductors which enable some of the most complex electronics seen today. In the past, vehicle electronics implemented flat architectures with isolated functions controlling various components of the power train and vehicle dynamics. These electronic systems communicated primarily through legacy bus interconnect protocols, like controller area network (CAN) and media-oriented systems transport (MOST) technologies.
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HDL DH FlexIP cores library:
MIPI IP Cores
JESD204B Tx, Rx
VbyOne IP core more >>
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Imagination's CXT GPU IP: The first mobile GPU core with ray tracing more >> |
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Register for Rambus + Siemens Live Webinar - Navigating the Intersection of Safety and Security
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Join us for this webinar where Thierry Kouthon of Rambus and Ann Keffer of Siemens will discuss hardware solutions for securing automotive electronics and how functional safety tools from Siemens meet the requirements of ISO 26262.
Register Now |
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The mmWave ASIC Enabler
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Robust OTP, MTP, Security IP
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Custom IO/ESD solutions
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The IP Boutique
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Highly scalable & ?exible silicon proven Security IP for embedded systems used in the connected world of the IoT. All turn-key solutions are compliant with most common industry standards (NIST and others). more >>
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16G Multiprotocol Serdes IP Core with different Interface protocols for...
The 16G Multiprotocol SerDes PHY IP Core supports PCIe 4.0, JESD204B, 10G ethernet, rapid IO, and CPRI protocols.
Cadence Ushers in New Era of Performance and Accuracy for Multiphysics...
Next-generation, high-order flow solver delivers up to 10X the accuracy of standard flow solvers
Synopsys Named a Leader in the 2022 Gartner Magic Quadrant for...
As the speed and complexity of development increases and the occurrence of high-impact application security breaches becomes more frequent, security and...
Rapid Silicon Licenses AndesCore D45 with DSP/SIMD extensions and...
The superscalar 8-stage D45 RISC-V Core will be hardened and embedded into an FPGA to provide a full-speed CPU.
Arteris IP FlexNoC Interconnect and Resilience Package Licensed in...
The goal of the project is to develop an accelerator chip for high-end deep learning applications that is a leap forward in terms of energy efficiency, reliability, robustness...
VeriSilicon Joins the Universal Chiplet Interconnect Express Industry...
Membership will drive VeriSilicons industrialization of chiplet-based projects and support aim of becoming a leading provider of commercialized chiplets...
SmartDV Expands Executive Team With McKenzie Ross as Vice President of...
Redoubled Focus on Branding and Marketing Strategy Will Fuel Companys Continued Growth
M31 Speeds Delivery of Silicon IP by 5X Using the Cadence Library...
Cadence solutions are production-proven, empowering the M31 engineering team to provide accurate, high-quality silicon IP to their customer...
Alma Technologies Launches Scalable Encoder and Decoder...
Fully compliant with VESA DSC 1.2b and backwards compatible with DSC 1.1
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Achieve dramatic functional verification productivity improvements with Avery Design System’s comprehensive and robust suite of industry leading VIP and complimentary solutions for emulation, prototyping, hardware/software co-verification to accelerate time to market and ensure functional correctness of your designs. more >>
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