Semiconductor IP News and Trends Blog

Makimoto’s Wave and the end of IP

Semiconductor engineers can only bend the laws of Physics so far. Will 20nm be the point where Makimoto’s Wave and Moore’s Law are no longer relevant? 

Physics is a cruel mistress. Engineers can bend her laws for only so long. The challenges faced by semiconductor manufacturers in the implementation of the 20nm geometry node will greatly impact the portability of design IP amongst different foundries. These challenges will have a big impact on IP design techniques and profitability for years to come.

Design reuse has long been seen as the most cost effective way to create and build ever more feature rich chips while driving down costs. But that paradigm may end at 20nm for reasons I’ll discuss shortly. Interestingly enough, this challenge to the cost efficiency of reuse will begin to occur during the peak of another paradigm shift predicted by Makimoto’s wave.

In 2012, the first 20nm chips and products will emerge from fabs like Globalfoundries and TSMC and IDMs like Intel. Next year also marks an inflection point for a predicted change in Makimoto’s Wave.

In the early 1990’s, Tsugio Makimoto of Sony Corp. developed a sinusoidal model to explain some of the cyclical nature of the semiconductor industry. Known as Makimoto’s Wave, the model consists of a 10-year cycle during which electronic products migrate from standard parts to custom devices before the process is reversed. The year 2012 will represent the change from a customization to a standardized cycle. This change will take 5 years, from 2012 to 2017 (see figure).

During this transition from customized to standard designs, one would expect to see fewer custom ASIC designs and more standard ASSP devices. Greater standardization has been synonymous with design reuse, the cornerstone of the semiconductor IP movement. One would then expect IP designs to accelerate in the new cycle of standardized devices.

But this time, Makimoto’s Wave may be slowed down by the same force that is affecting Moore’s Law, namely, the capability to manufacture transistors at the atomic level.

There are many reasons for the struggles faced by semiconductor IP providers at the 20nm node and beyond. Veteran EDA writer Ann Steffora-Mutschler provides a detailed summary of these challenges in her recent article, “20nm IP Portability Appears Virtually Impossible.” The main problem is the need for double-patterning (DP), which will be used in the manufacturing process until at least the 10nm node. “Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs,” notes Steffoa-Mutschler.

Most EDA vendors agreed that significant changes lie in store for IP designers at the 20nm node and beyond, mainly due to manufacturing issues such as DP, optical radius, OPC effects and others. These changes will make it very difficult for IP to remain context free, i.e., fab agnostic.

Will IP become a design paradigm of the past? Most experts think not. But they do believe that IP vendors will face increased expenses in porting IP between foundries.

Does this mean that foundries will become more involved in the creation of IP? Will increased IP costs mean that more designs will be done at lagging-edge IP-friendly nodes? This would have a significant slowing effect on Moore’s Law.

Manufacturing engineers have always been aware of the challenges faced in building chips at smaller and smaller process nodes. Designers began to feel this pain at 90nm and below, which is why Design-for-Manufacturing (DFM) and Design-for-Yield (DFY) tools became so popular. Now, even the IP community is starting to feel the manufacturers pain.