PipelineZero Architecture, hazards-free single-cycle execution, extreme code density, small silicon area, and power-saving design yield one of the most performance- and energy-efficient 32-bit processors available
Linley Processor Conference, Santa Clara, CA - October 22, 2014 - Wearable devices, Internet of Things (IoT) sensors, and other mobile products challenge the limits of modern processor efficiency, with features requiring significant processing capability but also demanding ultra-low energy consumption. A new 32-bit processor announced today by Beyond Semiconductor and CAST Inc. meets this challenge by combining state-of-the-art design techniques with an architectural feature seemingly drawn from the past: a zero-stage execution pipeline the companies call the PipelineZero Architecture.
The new BA20 PipelineZero 32-bit Embedded Processor IP Core is designed specifically for the most power-sensitive systems, where the usual low-power processor techniques fall short of reaching power targets. Operating at high efficiency with no wasted cycles and maximizing the work accomplished per energy consumed, the BA20 is a new sweet-spot processor for applications not requiring the high operating frequency of modern three- or five-stage pipelined processors. It delivers extremely competitive results for these applications, featuring:
Beyond Semiconductor achieved these results through design techniques already proven in the BA2X Processor Family combined with rigorous fine-grained optimizations to minimize switching plus the unique PipelineZero microarchitecture.
The BA20 Processor offers true single-cycle instruction execution of the BA2 Instruction Set, which reduces system-wide power usage through industry-leading extreme code density. The processors high level of performance efficiency means it can save energy by doing more in less timesleeping for more of the timeand by operating at lower clock rates. Built-in support for advanced power management techniques such as power and clock gating and dynamic frequency scaling further reduce energy consumption.
The BA20s PipelineZero Architecture provides zero-delay branches and no pipeline-stalling overheads. It:
Designers can optionally augment the processors capabilities with a hardware multiplier/divider, a multiply-accumulate block, and IEEE-754 compliant floating-point units. A vectored interrupt controller facilitates timely responses to interrupts, and an optional memory protection unit protects application code and/or data from corruption. The cores system interface uses a 32-bit wide AMBA AXI4-lite bus. Two tightly-coupled embedded memory (EMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.
The royalty-free BA20 Processor IP Core is available now in RTL source code or FPGA netlists, complete with the BeyondStudio Eclipse-based IDE. Various pre-integrated peripherals, memory controllers, and interconnects are available, as are a non-intrusive JTAG or serial debug package and ready-to-run reference design boards.
Attendees of the Linley Processor Conference can learn more about the new BA20 Processor in a presentation by CASTs Bill Finch at 1:20 pm on October 22, 2014.