Semiconductor IP News and Trends Blog

PCIe 4.0 Ecosystem with Synopsys and Mellanox

Synopsys has a long history of working with ecosystem partners as part of the development process, especially when new versions of a specification are rolled out. The PCIe 4.0 specification has taken a long time, but that hasn’t slowed us down. If you remember from previous postings, some of our PCIe 4.0 demos include:

• The world’s first PCIe Gen4 system is comprised of a Synopsys PCIe Gen4 Root Complex talking to a Synopsys PCIe Gen4 Endpoint (both of which have passed PCI-SIG compliance testing at Gen3 by the way).
• PCI Express 4.0 Performance at More than 1600 MB/s. This demonstration features Synopsys’ DesignWare® Controller and PHY IP for PCI Express® 4.0 solution and uses a PCI Express switch to connect a host PC to an Endpoint application. Since today’s PCs do not support PCIe® 4.0 at 16 GT/s, the switch utilizes four lanes at 5 GT/s connection on the upstream port
• PCI Express 4.0 interoperability between Synopsys and Teledyne-LeCroy. This demonstration shows interoperability between the Synopsys DesignWare IP for PCI Express 4.0 and Teledyne LeCroy Z416 Protocol Analyzer/Exerciser – an industry first. This indicates the IP is working as expected and meets the requirements of the latest PCI Express specification.

This brings us to our latest news, today, June 5th, 2017, we announced Synopsys and Mellanox Demonstrate Complete PCI Express 4.0 Host and Device System Interoperability. Please go to the link to read the full press release, but some of the highlights of our announcement:

• The host, including the DesignWare Root Complex IP for PCI Express 4.0 specification, executes full initialization across the PCI Express link at 16 GT/s with the Mellanox ConnectX-5 Ethernet and InfiniBand network adapter
• Lane margining exercised to provide visibility into the link quality, enabling more robust, high-performance systems
• Demonstration utilizes the DesignWare IP Prototyping Kit for PCI Express 4.0 Root Complex, enabling fast prototyping, SoC integration and software development
• Demonstration will be presented at PCI-SIG Developers Conference in Santa Clara, CA, June 7-8, 2017, in Synopsys Booth #2

Synopsys and Mellanox have a long history of collaboration to drive development of the PCI Express 4.0 specification for the benefit of the industry. Both companies contributed the PHY characterization data to validate the electrical requirements of the PCI Express 4.0 specification at 16 GT/s. The companies began demonstrating PCI Express 4.0 PHY electrical interoperability in 2015 and are now demonstrating full system interoperability for the PCI Express 4.0 specification at 16 GT/s. Please stop by our booth to see the demo at PCI-SIG this week.

About the Authors

Scott Knowlton

I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

Richard Solomon

I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I’ve also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.