Deployment of Artificial Intelligence (AI) and edge compute is driving a paradigm shift in hyperscale data centers. Trends such as 5G for AI-powered IoT edge applications, large amount of data for video streaming, and zettabytes of data for fully autonomous vehicles, have required hyperscale data centers to support exponential growth of data volume and implement distributed low-latency processing. Such trends have also led to more complex and expensive data center storage architectures which are required to support a combination of hard drives and solid-state drives (SSDs), configured with varying interfaces and targeting different workloads. This article explains how to use PCI Express (PCIe) 5.0/6.0 PHY IP to enable U.2/U.3 connectivity in their data center storage designs.
Evolution of Storage Architectures
One major challenge that system companies face while designing servers is upgrading the storage architecture to meet present and future data center requirements. The upgrade includes integration of multiple backplanes, mid planes and controllers, all of which increase system complexity and cost.
One way to address this challenge is to optimize storage architecture by implementing drive consolidation, supporting all three SSD protocols (Serial Attached SCSI (SAS), SATA and NVMe) with one common infrastructure.
Initially, SAS interface allowed SATA SSDs/HDDs (hard disc drives) to interoperate with SAS backplane, HBAs (Host Bus Adapters) or RAID (Redundant Array of Independendent Disks) controllers. However, support was unavailable for NVMe SSDs, which required a separate configuration that utilized an NVMe-enabled backplane.
Figure 1 shows the server storage architectures of today and past including three components –backplane, expander or mid-plane and controller.
Figure 1: Storage architecture requiring different backplanes for SAS, SATA and NVMe
The advent of the U.2 specification based on SFF-8639 form factor was the first step towards storage drive consolidation. The U.2 form factor supports up to four lanes of PCI Express (PCIe) for NVMe SSDs, and up to two lanes for SAS/SATA SSDs/HDDs, as shown in Figure 2. Even though U.2 supported all three drive interfaces, NVMe, SAS and SATA, it was not optimized since it did not provide interchangeable SAS/SATA/NVMe support in the same slot. It still required a separate backplane, mid-plane and controller for NVMe.
Figure 2: The U.2 form factor supports up to 4 lanes of PCIe for NVMe SSDs and up to 2 lanes of SAS/SATA SSDs/HDDs
The storage architecture further evolved with the advent of the U.3 specification, which is built on the SFF-8639 connector.U.3 provides true storage drive consolidation by supporting all three drive interfaces in the same server slot using 1 backplane, 1 mid-plane and 1 controller as shown in Figure 3. U.3 was developed by the Storage Networking Industry Association (SNIA) SSD Form Factor (SFF) Technical Affiliate (TA) and defined by the SFF-TA-1001 specification. It is also backward compatible with U.2, but U.2 is not compatible with U.3 hosts.
Figure 3: The U.3 specification supports 1 backplane, 1 mid-plane and 1 controller to provide true interface drive consolidation
The U.3 specification primarily includes a tri-mode controller, SFF-8639 connector and a Universal Backplane Management.
- Tri-mode Controller: Forms an interface between server host and universal backplane. It supports respective protocols for SAS, SATA and NVMe drives, providing server system companies a consolidated solution instead of using separate controllers for SAS/SATA and NVMe. This provides flexibility and allows blending the drives as per the end application requirement.
- SFF-8639 Connector: This connector is situated on the drive bays and connects SAS, SATA and NVMe drives to the tri-mode controller. The host detects a compatible protocol for communication. The SFF-8639 connector uses a combination of available pins to identify which drive is present. U.3’s storage drive consolidation capability enables server system companies to simplify their backplane designs by using a single connector to support SAS/SATA and NVMe drives, as shown in Figure 4. This also results in cost benefits due to utilization of fewer components.
Figure 4: U.3 connector supports SAS, SATA and NVMe drives
- Universal Backplane Management (UBM): Developed by the SSD Form Factor Working Group and defined by the SFF-TA-1005 specification, UBM provides a standard method for managing and controlling SAS, SATA and NVMe backplanes, providing configurability and flexibility. UBM enables two important aspects of backplane management:
- Support interchangeability between storage media types within a drive bay, for instance changing between SAS, SATA and NVMe while the system is running
- Ability to manage SAS, SATA and NVMe devices without any changes to storage drives or software stacks
Advantages of U.3
The U.3 specification provides multiple advantages:
- Provides higher flexibility and configurability with reduced system complexity and cost, for consolidation of SAS, SATA and NVMe drives and simplifying the system with cost-effective cables and components
- Enables implementation of SAS, SATA and NVMe protocols through a single drive slot
- Enables standard management tools across server storage protocols
- Consolidates the benefits of SAS, SATA and NVMe drives for better performance
- Offers the option to support NVMe, which is gaining traction over SAS and SATA
- Maintains backward compatibility to U.2
PCIe PHY IP support for U.2/U.3 form factors
The enterprise storage is migrating from SATA to NVMe due to benefits like scalability and lowest latency. This is fueled by the requirement of hyperscale data centers to have operational data on faster storage such as NVMe SSDs with PCIe PHY interface, which is supported by U.2/U.3 architecture. PCIe 4.0 PHY IP is already deployed in NVMe SSDs and PCIe 5.0 is becoming the prominent interface for this implementation as the performance requirement is doubling from 16GT/s to 32GT/s.
As shown in Figure 5, a customized, area-optimized, 6-lane PCIe 5.0 PHY solution can be used to support U.2/U.3 connectivity with features that include:
- Reference clock detection circuit with hysteresis and a digital clock edge counter
- Support for 25MHz reference clock
- Spread spectrum clocking (SSC) and Separate Refclk Independent SSC (SRIS) for 25MHz reference clock
- A unified PCS wrapper with bifurcation Mux and any lane to any Mux
The leading storage companies are already using such solution.
Figure 5: Customized PCIe 5.0 PHY for U.2/U.3 connectivity
SSD companies are already designing PCIe 6.0 PHY + Compute Express Link (CXL) IP solutions for U.2/U.3 connectivity. PCIe 6.0 PHY IP will improve memory bandwidth, CXL IP will lead to development of new storage architectures as it will enable storage systems to take advantage of much larger memory pools for caching.
With the exponential increase in data volume and complexity, hyperscale data centers are going through a paradigm shift, incorporating distributed low latency processing. Implementation of U.2/U.3 storage architecture is critical for these data centers as it enables varying workloads with optimized performance and cost. The U.3 standard ensures that the storage is designed to meet present and future data center requirements. The specification supports SAS, SATA and NVMe drives, in the same server slot using 1 backplane, 1 mid-plane and 1 controller. In addition to system flexibility, the U.3 specification also provides a replacement path between SAS, SATA and NVMe. U.3 results in simplified backplane system and reduction in total cost of ownership due to fewer traces, cables and connectors. It also maintains backward compatibility with U.2 platform. To easily enable U.2/U.3 connectivity, designer can integrate Synopsys’ DesignWare IP for PCIe 5.0, PCIe 6.0 and CXL. The available Synopsys DesignWare IP for PCIe 5.0 offers a customized x6-lane solution, enabling U.2/U.3 formfactors. Designers can leverage Synopsys’ DesignWare IP for PCIe 6.0 to address future requirements for U.2/U.3. Synopsys offers a complete PCIe controller, PHY and verification IP solution that is silicon proven and have achieved successful interoperability with third-party devices. The solution is optimized to meet latency, area, and power requirements of the target application.