Semiconductor IP News and Trends Blog
PSS this week
Busy and exciting times for the Cadence PSS team and I stepped out of the routine to write something about it. We just finished a successful evaluation at TI Israel. A power verification and validation team introduced to us a state-of-the-art UVM-e testbench with seven levels of nested module-UVCs(!). It took only four days to co-create the behavioral model, run scenarios and achieve our goals. The options in PSS are really endless and the amount of value that can be achieved so quickly is always surprising to users.
In between, I got a chance to present and attend PSS sessions at the Cadence ClubV conference. Alex Levin (Intel) delivered a presentation called “Content development With Portable stimulus“ that was co-written with Ramon Chemel (also an active member of the Accellera PSS working group). It talked about integration content creation, with the challenges of coordinating system shut-down, including IPs and cores, with fine control over the power-states, traffic, wake-up reasons, and more. The beauty of this model was its reusability. Leveraging the powerful semantics of PSS, they defined a generic frame-work that allows creating sophisticated-automated abstract scenarios. Via registrations of IPs, cores and power transition actions, the abstract scenarios can be mapped and serve any system with any IPs. I have seen in the past users struggling for more than a year with these kinds of challenges, which these guys solved brilliantly and elegantly. If this is relevant to you, I highly recommend getting these slides.
The previous week, we had a PSS-UVM synergy event at the Cadence office in Bangalore. You can definitely find good papers on the PSS-UVM topic, but they typically re-iterate the high-level value with supporting visualization, without showing a real-demo or implementation code. At the event, we described and showed two running demos. The first was focused on the coverage maximization of hard-to-achieve scenarios. In the second demo, we focused on the methodology and mechanics of connecting PSS to your existing UVM SystemVerilog environment. For this purpose, we used the good-old UBUS golden-example that is part of UVM. We reviewed the methodology and the code needed to connect PSS to UVM sequences and other SV tasks. We spent a little bit of time on controlling the UVM build phase, threads control and more. After simulating the demo on a UVM transactional setup, we modified the target-template attribute to embedded (the attribute is part of our recommended methodology) and executed the same scenarios in embedded SW.
At the same Bangalore event, a user key-note described how he was able to leverage PSS to cut his project deadlines from a year and a half to three-four months. One of his key points was that at the end of the day it is the intent and your talent that matters. I cannot agree more on this point and decided to dedicate the technical part of the blog to this statement. Some people say that they can auto-extract coverage goals from the generation model. I think that we need to take coverage more seriously than that. Observe the following simple state-machine of a power controller:
This example is straight forward to describe in PSS. but let’s assume that we can build a generic technology that can extract coverage from the PSS generation model. What coverage should it produce? Of course, we can have an endless amount of legal power-transition chains. Some of these are of extreme importance, but many are not interesting, not practical, and a repetition of what was already tested in other chains. Also, the bugs in such systems may hide in scenarios where reset comes in different power states, while the DUT is busy with critical operations, or while a programmed transition is taking place. PSS allows setting the goals easily. PSS functional coverage requires one line to define a cover item for all power states or all transitions, but this is just the basics of the basics. PSS allows setting sophisticated scenarios as coverage goals. It can include ordering and timing, be leveraged on all platforms, and be used to remove redundancy within individual tests or at the regression level. Let us know if you wish to know more about how this can be achieved.
Coverage is a key pillar of automated verification that shrinks deadlines and improve qualify. If you wish to be somewhat serious about it, no language or tool can replace using talent and gut-feeling to explore the cracks in your system. Let us know if you wish to learn more on how PSS and Perspec allow efficient setting and hitting your intent-driven verification goals.