Semiconductor IP News and Trends Blog
Popular Accellera Day Kicks Off DVCon 2019
The first day of the Design and Verification Conference and Exhibition (DVCon) is dedicated to updates and short tutorials from the standards body that supports it – Accellera Systems Initiative.
By John Blyler, Editor, JB Systems
The time is quickly approaching for the annual gathering of engineers, managers and professionals involved in the high-tech world of system-on-chip (SoC) design and verification. The gathering is collectively centered around DVCon U.S., which runs from February 25-28, 2019 at the Hilton DoubleTree Hotel in San Jose, CA.
Figure: Participants in a panel session at DVCon 2018.
Though it may seem to be a niche event to outsiders, DVCon is an important and respected conference to electronic design and automation (EDA) tool vendors and related semiconductor suppliers. This year’s offering of content, presentations, technical sessions and exhibitions builds on that reputation.
What’s come to be known as “Accellera Day” will kick off the first day of the conference (Monday, 2/25). Tutorials, short workshops and a free luncheon panel discussion provide the venues to highlight the latest technical updates and practical case studies on standards that affect the worldwide SoC electronics industry.
The morning will start with a tutorial presented by Cliff Cummings on the changes and features in the new IEEE 1800.2 Standard for UVM. The tutorial will be followed by a luncheon event hosted by Accellera chair Lu Dai, who will provide an update on the organization’s critical activities. Next, a brief 2019 Technical Excellence Award presentation will lead into an interactive SystemC panel that explores what’s next for the standard. The panel will consist of familiar participants from Mentor, A Siemens Business, Synopsys, Cadence and NVIDIA.
The afternoon will be dedicated to short workshops focused on high-level synthesis, verification, deep learning, portable testing and stimulus, security and more (see below for details).
Topping off a day of meaningful technical talks will be the opportunity to relax and network during the DVCon reception (5 to 7pm). So come for the education but stay for the mingling!
1:45pm to 3:15pm
- Focusing on High-Level Synthesis and Functional Coverage for SystemC
- Formal Verification Bootcamp
- Deep Learning for Engineers
3:30pm to 5:00pm
- Going Practical with the Portable Test and Stimulus Standard (PSS)
- System-Level Security Verification Starts with the Hardware Root of Trust
- It’s Been 24 Hours – Should I Kill My Formal Run?