Semiconductor IP News and Trends Blog

RISC-V, Open Source Hardware and CHIPS Trends

The end of 2019 and start of 2020 witnessed a flurry of activities in the RISC-V and Open Source hardware and software communities.

In December, the OpenHW Group announced the CORE-V Chassis SoC project, which include the CORE-V family of open-source RISC-V cores. These IP cores and associated tools consist of a Linux capable 64-bit processor coupled with a 32-bit coprocessor and are intended to accelerate the design process and ensure manufacturability of high-volume chip production (see Figure 1).

To date, no processors have been manufactured. The recently formed OpenHW Group plans to tape out a multi-core processor evaluation system-on-chip (SoC), capable of running the Linux operating system, during the 2nd half of 2020. As mentioned above, the CORE-V Chassis will use a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core. The 64-bit CV64A core is based on ETH Zurich’s Ariane implementation of its RV64GC RISC-V core IP. RV64GC is also used by many other RISC-V projects, including the chip start-up SiFive’s U54.

Figure 1: OpenHW Group / Core-V Chassis

The OpenHW Group is a relatively new not-for-profit global organization that wants to aid the adoption of open-source processors by, “providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.” Inaugural OpenHW sponsors include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich (University), GreenWaves, Imperas, Metrics, Mythic, NXP, Onespin, Silicon Labs and Thales.

The advent of open instruction set architectures (ISAs) IP such as RISC-V has encouraged the momentum for open-source hardware processor development. The OpenHW Group aims to drive greater awareness, understanding and availability of open-source processor implementations.

ISA Basics

It’s important to note that the RISC-V is not a processor. In actuality, RISC-V is a free, open-source instruction set architecture (ISA) that is based on reduced instruction set computer (RISC) principles. So what’s an ISA?

Specifically, an ISA is an abstracted model of a computer. A processor is an implementation of an ISA.  It is the part of the processor that is visible to the programmer or compiler writer. An ISA is analogous to a human language but instead of communication from person to person the ISA enables communication between the hardware and software of a processor.

The ISA represents the primitive operations of the processing machine that are available for use by assembly programmers and compiler writers. One of the main functions of a compiler is to allow a programmer to write an algorithm in a high-level language without having to care about CPU-specific instructions.

Figure 2: Instruction Set Architecture (ISA)

Each processor has its own ISA, be it from ARM, Intel, AMD, nVidia, etc. However, unlike the proprietary ISAs for these commercial processors, anyone can use the open-source RISC-V ISA for free. They can use it as the basis for their own processor implementation, rather than pay fees for the commercial processors. In other words, anyone can use the RISC-V ISA to make in-house processor implementations to sell as an off-the-shelf physical device or license as IP cores that can be used in the SoC designs of others.

Commercial Processor IP

So how do commercial vendors of processor IP feel about this open source ISA and processor implementation movement? Generally, not so great. The allure of the RISC-V is the ability to develop one’s own application-specific SoC without having to pay an upfront fee. This means the cost of entry is lower but not zero. Users will still have to pay for the costs of tools, test, and verification to add the processor IP to their design but there will be no license fee for the ISA itself. This is where the pain point will be for companies like ARM and others.

Will Arm’s business model have to change? The answer depends upon whom you ask. But the open architecture approach will certainly be appealing to many customers. The big issue that Arm reminds users is the hidden open-source cost of verifying and implementing the instruction set and processor architecture. Arm notes that they have a very stable and mature ecosystem that supports their processor development system, whereas open source does not – at least, not yet.

Still, the open source model has been well validated over the years. RISC-V is getting a lot of attention in the technical community. The addition of open source hardware adds a new incentive to the ISA / processor IP equation.

CHIPS

Momentum continues to grow for the open source instruction set architecture RISC-V. Last year, SiFive – a startup built around the RISC-V – sold out all of its single-board “HiFive Unleased” computers for RISC-V developers. Shortly thereafter, Western Digital signed a multi-year license for the SiFive Freedom Platform. The RISC-V ISA appears to have growing support from hardware manufacturers, especially those building embedded IoT or edge devices.

Another interesting development has been the recent creation of the CHIPS Alliance by the normally software-focused Linux Foundation (see Figure 3). The CHIPS Alliance project is tasked with hosting implementation efforts – i.e., hardware processors – around the RISC-V ISA, with an initial membership roll that includes SiFive, Esperanto Technologies, Western Digital, and Google.

Figure 3: CHIPS Alliance

One of the newest editions to the ecosystem is France-based Cortus. Like SiFive, Cortus is a founding member of the RISC-V foundation. Both companies have the expertise necessary to turn designs into manufacturable products. Last year, Cortus announced the availability of a family of six RISC-V processors that its customers can use to design into application-specific integrated circuits.

2020 is definitely shaping up to be the year of the open source chip!