Chip Signal
ChipEstimate.com - Chip Planning Portal
  • English
    • English
    • Japanese
    • Chinese
  • Log In
    • Log In
    • Register
    • Partner Login
  • Search IP
    • Advanced Search
    • Request IP
    • Browse IP
    • Compare IP
    • IP Vendor List
    • Verification IP
    • FPGA
  • IP Vendors
    • IP Vendors
    • TSMC
    • GLOBALFOUNDRIES
    • SMIC
    • Common Platform
    • Verification IP
    • Cadence
    • FPGA
    • Non-Commercial IP
  • IP Resources
    • Compare IP
    • White Papers
    • Tech Talks
    • Videos
    • Blogs
    • Newsletters
    • Headline News
    • Industry Trends
  • Partners
    • Overview
    • Join
    • Login
  • Support
    • Support
    • Contact Us
    • My Account
  • About Us
    • Overview
    • Contact Us
  • Log In
  • English
    • English
    • Japanese
    • Chinese
  • Search IP
    • Advanced Search
    • Request IP
    • Browse IP
    • Compare IP
    • IP Vendor List
    • Verification IP
    • FPGA
  • IP Vendors
    • IP Vendors
    • Common Platform
    • GLOBALFOUNDRIES
    • SMIC
    • TSMC
    • Cadence
    • FPGA
    • Non-Commercial IP
  • IP Resources
    • Compare IP
    • White Papers
    • Tech Talks
    • Videos
    • Blogs
    • Newsletters
    • Headline News
    • Industry Trends
  • Partners
    • Overview
    • Join
    • Login
  • Support
    • Support
    • Contact Us
    • My Account
    • Do Not Sell My Info
  • About Us
    • Overview
    • Contact Us
Industry News
the latest top stories
Search
World’s Most Trusted IP Resource

Industry News

Rambus Completes Acquisition of Hardent

Strengthens CXL Memory Interconnect Initiative and accelerates roadmap of data center solutions

SAN JOSE, Calif. – May 24, 2022 – Rambus Inc.(NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, today announced the completion of the acquisition of Hardent, Inc. (“Hardent”), a leading SoC digital design company. CXL-based architectures will be critical to meet the increasing demands of cloud data centers. CXL memory expansion and pooling promise significant improvements in per-core memory performance and capacity for data-intensive workloads like AI/ML, and will deliver new efficiencies at scale through composable infrastructure. With extensive semiconductor experience, Hardent’s design expertise in advanced SoCs enhances the world-class Rambus engineering team and provides key resources to strengthen the Rambus CXL Memory Interconnect Initiative.

“Rambus is dedicated to advancing the new era of data center architectures, and ongoing investment and innovation in CXL-based solutions are key focus areas in our strategy,” said Luc Seraphin, president and CEO of Rambus. “Hardent’s advanced SoC design experience amplifies our CXL development efforts, and we are very pleased to welcome our new colleagues to the Rambus team.”

This transaction will not materially impact 2022 financial results.

For more information, visit rambus.com/hardent.

Press Contact:
Cori Pasinetti
Rambus Corporate Communications
t: (650) 309-6226
cpasinetti@rambus.com

Forward-looking statements

Information set forth in this press release, including statements related to the potential of Hardent’s technology for Rambus and its roadmap, and the effects of the acquisition, constitute forward-looking statements within the meaning of the safe harbor provisions of the Private Securities Litigation Reform Act of 1995.

These statements are based on various assumptions and the current expectations of the management of Rambus and may not be accurate because of risks and uncertainties surrounding these assumptions and expectations. Factors listed below, as well as other factors, may cause actual results to differ significantly from these forward-looking statements. There is no guarantee that any of the events anticipated by these forward-looking statements will occur, or what effect they will have on the operations or financial condition of Rambus. Forward-looking statements included herein are made as of the date hereof, and Rambus undertakes no obligation to publicly update or revise any forward-looking statement unless required to do so by federal securities laws.

Major risks, uncertainties and assumptions include, but are not limited to: the expected benefits and costs of the transaction; management’s plans relating to the transaction; the potential benefits, costs and results of CXL memory expansion and pooling; plans, strategies and objectives of Rambus for future operations; the successful integration of Hardent; Rambus’ anticipated operational and financial results, expected market share growth, and successful product development; the risk that disruptions from the transaction will harm Rambus’ business; and other factors described under “Risk Factors” in Rambus’ Annual Report on Form 10-K and Quarterly Reports on Form 10-Q; and any statements of assumptions underlying any of the foregoing. It is not possible to predict or identify all such factors. Consequently, while the list of factors presented here is considered representative, no such list should be considered to be a complete statement of all potential risks and uncertainties.

Brought to you by ChipEstimate.com



Rambus IP Catalog
View All

Other Top Stories

  • Cadence Advances Radar, Lidar and Communications Processing for ...
  • Synopsys and Arm Strengthen Partnership to Advance Next-Gen Mobile ...
  • VIDATRONIC ANNOUNCES POWER MANAGEMENT IP NOW CERTIFIED ON ...
  • UMC, eMemory, and PUFsecurity Announce Successful Silicon-Proven ...
  • FLEX LOGIX AND CEVA ANNOUNCE FIRST WORKING SILICON OF A DSP WITH ...
  • New Cadence Xcelium Apps Accelerate Simulation-Based Verification ...
View All

Latest IP

    SMIC15LV_MC

    VeriSilicon

    SMIC25 MC

    VeriSilicon

    SMIC09LL 9T HVT STD Cells

    VeriSilicon

    SMIC09LL 9T RVT STD Cells

    VeriSilicon

    SMSB11ULL

    VeriSilicon
View All

Blogs

Demystifying CXL.cache

Demystifying CXL.cache

By Sangeeta Soni Posted 5.13.2022
If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you ...
System Verification Scoreboard: Its Role and Partnership with Verification IPs

System Verification Scoreboard: Its Role and Partnership with Verification IPs

By Dimitry Pavlovsky Posted 4.29.2022
As discussed in the last installment of the blog, a robust system level scoreboard is esse...
Search IP
Advanced
Request IP
Browse IP
Compare IP
IP Vendor List
Verification IP
FPGA
IP Vendors
All Vendors
FPGA
Non-Commercial IP
Foundries
TSMC
GLOBALFOUNDRIES
SMIC
Common Platform
IP Resources
Compare IP
White Papers
Tech Talks
Videos
Blogs
Newsletter
Headline News
DAC - IP Talks
Industry Trends
Partners
Overview
Join
Login
Support
Support
Contact Us
My Account
Do Not Sell My Info
About Us
Overview
Contact Us
ChipEstimate.com Chip Planning & IP Portal -- Copyright © ChipEstimate.com. All rights reserved.
Privacy Policy Terms of Use