July 5, 2022
Seeing what's not there. IMG Series 4 NNA meets Visidon's deep-learning-based Super Resolution technology.

Alex Pim
Imagination Technologies
Last year I read a fascinating article on LinkedIn about using deep-learning-based super-resolution networks to increase the apparent detail contained in images and videos sent back by Nasa's Perseverance Rover. This article got me thinking about how, when I first watched Blade Runner in the 90s, scenes such as "enhance 15 to 23" seemed so implausible based on the technology available at that time. At that point (and because of films like Blade Runner) I was embarking on a three-year degree course in artificial intelligence and I could not have predicted the impact of the deep learning revolution at the start of the millennium. more >>
Mixel MIPI D-PHY, C-PHY, and M-PHY are silicon-proven and available now. more >>
Imagination's CXT GPU IP: The first mobile GPU core with ray tracing more >>
The 802.11n/ac/ax LDPC decoder is developed for high...
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TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
from True Circuits
TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps
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Wi-Fi 802.11 ax /Bluetooth LE...
from T2M
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in TSMC...
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eSPI & SPI Master / Slave Controller w/FIFO (APB,...
from Digital Blocks
Weasic 8-16GHz 24-bit Fractional-N synthesizer w/ integrated VCOs
Standard Cell 7-track
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General Purpose I/O
from M31 Technology Corporation
Huali 28nm HKCP process Multiple Power Supply IO library
from VeriSilicon
GLOBALFOUNDARIES 22nm FDSOI LVDS Transceiver Pad from VeriSilicon
1Kbyte Embedded EEPROM with configuration 64p8w16bit from NTLab
512-bit EEPROM from NTLab
ST 6-bit, 20 GSPS Analog to Digital Converter IP block
from Alphacore
HDMI 2.1 Forward Error Correction (FEC) Receiver from Rambus
HDMI 2.1 Forward Error Correction (FEC) Transmitter from Rambus
Path Margin Monitor IP
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ISP (Image Signal Processor) with the minimum...
from Shikino High-Tech
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Path Margin Monitor IP
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TSMC CLN7FFLVT 7nm Clock Generator PLL - 300MHz-1500MHz
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12-bit, High Speed Current Steering DAC in TSMC (65nm, 40nm, 28nm,...
from Synopsys
1-cluster 4ppcPowerVRSeries8XEP GPU including Vulkan, OpenGL ES...
from Imagination Technologies
TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps
from True Circuits
ISDB-S3 Demodulator and Decoder IP (Silicon...
from T2M
10/100/1GMAC Ethernet Controller
from Mobiveil
10/100/1000 Mbps Triple-Speed Ethernet MAC from Mentor
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Heading to DAC next week in San Francisco? Stop by & visit Silicon Creations, booth #1338 to learn more about our world class IP. more >>
Cadence Advances Radar, Lidar and Communications Processing for...
New Tensilica ConnX 110 and ConnX 120 DSPs Provide Optimal PPA and More Flexible Compute Options
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GbE (10/100/1000 Base-T) PHY IP licensed by 3...
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Analog/Mixed Signal Lunch Panel at the 59th DAC
Accellera invites you to a luncheon and panel discussion focused on the current state of analog/mixed-signal standards, the challenges, and the opportunities.
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Cadence verification flow lets customers improve verification throughput and achieve advanced software debug
Achieve dramatic functional verification productivity improvements with Avery Design System’s comprehensive and robust suite of industry leading VIP and complimentary solutions for emulation, prototyping, hardware/software co-verification to accelerate time to market and ensure functional correctness of your designs. more >>
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