Semiconductor IP News and Trends Blog

Semi-IP News – Dec 2015

Puzzle solving with EDA tools; abstracting synthesis and verif.; IP of IoT;  cyber-attacks via DRAM, SoC power; RFIC IP; and SoC’s supplanting PCBs; and more.

By John Blyler and Blake Loentrau,  JB Systems

Puzzle solving via constraint engines has been in the air recently.  Sandeep Gor of DigitialVerification proposed a challenge to e-speakers to solve Einstein’s five house problem. Soon thereafter, EDA tool vendor Amiq published their solution.

Remember when RTL co-design and co-verification where the prolific buzz words? Today’s chip design space prefers the nomenclature of high-level synthesis (HLS) and high-level verification (HLV), as shown in a Calypto whitepaper on the design of ASIC IP at higher levels of abstraction. Qualcomm’s HLS/HLV flow was applied to Calypto’s HLS/HLV technology (flow vs. technology?) on smartphone and image processing IP designs.

In this month’s travelogue, publisher John Blyler talks with Chipestimate.TV director Sean O’Kane about the recent Renesas DevCon and trends in software security patches, hardware-software platforms, small to medium businesses creating System-on-Chips, intellectual property (IP) in the Internet-of-Things (IoT) and systems engineering management.

Researchers at Graz University of Tehcnology outline how Intel processor enabled machines can be attacked via DRAM accesses.

In preparation for the ubiquitous IoT, UltraSoC has announced technology that repurposes the debug and monitoring devices on their SoC platform as security monitors.

Tony King-Smith of Imagination Technologies discusses the need for RF IC designers, IP platforms, IoT as the new embedded and fabric-based SoCs.

Researchers at Graz University of Tehcnology outline how Intel processor enabled machines can be attacked via DRAM accesses.

According to a recent ARM whitepaper, SoCs have reached a price-point competitive with discrete component PCBs and analyzes the economics behind the trend.

EE Journal’s Kevin Morris thinks about integration on a company rather than design scale.

Meanwhile Tudor Timi—in preparation for DVCon Europe—was hard at work on finding the number of combinations possible for AHB bus wrapping.  He started using the SV constraint solver, but eventually wrung the full solution out with the help of Prolog.

Benchmark’s, they’re not just for desktop processors anymore. Ambiq discusses the Embedded Microprocessor Benchmark Consortium.

Verifworks discusses the recent port of their third-party EDA tools and provides a glimpse into the Verdi open debug platform.

Cadence presented a nice high-level backgrounder on the history of the SoC power-problem, and the methods that have been developed in response to it.  It has a bit of a plug at the end, but what corporate blog doesn’t?

Invionics—a provider of EDA tools used in building… wait for it… EDA tools—hosts an interesting blog series of blogs related to all things EDA.  This particular post covers the differences between SystemVerilog’s assign and alias statements.