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Complex Chip Design - Clearing the Final Hurdle Using Post-Silicon Verification IP

Verification is one of the most critical and complex activities that occurs throughout the process of designing an SoC or ASIC device. It is typically acts as the gatekeeper at each stage of the process as the design transitions from a high-level description to a detailed layout of the chip. The final hurdle of the project requires verifying the prototype silicon device (or an FPGA programmed with the final design) before committing to volume manufacturing. This critical step is the final test to make sure that the device meets all specifications for functionality and performance before releasing the final device to production.  

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