Semiconductor IP News and Trends Blog
Taking LPDDR5 to the Next Level
To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies supported by its latest low power memory offering LPDDR5 to include the 937MHz and 1066MHz that translates to the max data rates of 7500MT/s and 8533 MT/s.
Devices supporting these incredibly high data rates are being categorized as LPDDR5X SDRAM devices. To support these high speeds whiles still keeping the real DRAM hardware complexity in check, lot of work has been done by JEDEC member companies including Cadence as an active JEDEC member.
Here is the list of key differences that LPDDR5X SDRAM devices have over LPDDR5 SDRAM:
- To Improve READ SI performance in the dual rank system at high speeds that Lpddr5X devices support a Unified NT-ODT Behavior has been defined. Unified NT-ODT is a requirement for all LPDDR5X devices
- To support high data rates for Lpddr5X, we need a way to compensate for transmission loss. This has been achieved by defining the pre-emphasis function. Lpddr5X devices have pull up or down pre-emphasis for each of the lower/upper byte lane programming.
- Rx Offset Calibration Training – LPDDR5X SDRAM provides Offset Calibration Training for adjusting DQ Rx offset and Offset Calibration Training is recommended for every power-up and initialization training sequence to cope with the SDRAM operating condition change
- Extended Latencies – LPDDR5X SDRAM devices support extended Read, Write, nWR, ODTLon and ODTLoff Latency Values to account for longer number of cycle it takes to do the data access to memory array. WCK2CK Sync AC Parameters are also extended.
- LPDDR5X SDRAM Devices support Per-pin controlled Decision Feedback Equalization: DFE. This includes new Mode Registers 70/71/72/73/74.
- New LPDDR5X SDRAM Device specific Clock AC Timings for 937.5/1066.5MHz and Write Clock AC Timings for 3750/4266.5MHz.
- New Mode register fields or additional conditions on the use of existing fields have been added to several Mode registers for LPDDR5X devices. Some of the examples of changed MR are MR0, MR1, MR2, MR13, MR15, MR41, MR58, MR69, etc.
- LPDDR5X SDRAM devices do not support 8 Bank Mode of operations. 8 Bank Mode doesn’t offer the architectural benefit of more bank interleaving resources and core operation timings at high speed that 16B and BG Mode have. It is specially limiting for high speed LPDDR5X devices support leading JEDEC to drop 8 Bank Mode support for LPDDR5X.
Overall LPDDR5X SDRAM is one of the fastest DRAM memories supported currently with Data rates of 8533 MT/s.
Cadence MMAV VIPs for LPDDR5 and LPDDR5X are compressive VIP solutions and support all of the above-listed LPDDR5X features. LPDDR5X is still being worked upon so we may see additional features being added to it in 2021 and Cadence is actively tracking the development of the LPDDR5X standard at JEDEC.
More information on Cadence LPDDR5 VIP is available at the Cadence VIP Memory Models Website.