White Papers
Bridging SoC Architectures for Faster Timing Closure
The complexities of SoC timing closure are addressed in two fundamental ways today. The first is to continue to utilize new EDA tools in the design flow that improve simulation and analysis. A second way is to use architecture tools that help better predict behavior of key elements before the chip design begins, such as data flows and IP interoperability, in order to mitigate timing closure risks before the chip is designed. Some companies today use both.
But given the levels of extreme complexity now on a single chip, and analyzing the directions that both the EDA and IP providers are taking to support each of the methodologies highlighted briefly above, is it time to revisit the basic architecture philosophies used for SoCs? And how does this help the timing closure problem?
To see the entire IP Doc from Phil Casini, TekStart LLC, please log in or register.
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