Bridging SoC Architectures for Faster Timing Closure
The complexities of SoC timing closure are addressed in two fundamental ways today. The first is to continue to utilize new EDA tools in the design flow that improve simulation and analysis. A second way is to use architecture tools that help better predict behavior of key elements before the chip design begins, such as data flows and IP interoperability, in order to mitigate timing closure risks before the chip is designed. Some companies today use both.
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