Tiempo, located near Grenoble (France), develops and commercializes a complete solution - IPs and synthesis tool for the design of innovative asynchronous integrated circuits.
Crypto-processor cores: DES, 3DES, AES, RSA and ECC. Highly secured and ultra-low power.
Microcontroller cores: TAM16 (16 bits) and TAM32 (32 bit) microcontrollers with customizable instruction set and SDK. Ultra-low power, ultra-low and variable voltage, immediate sleep / wake-up and secured.
Tiempo solution allows semiconductor companies to:
Design complex chips with ultra low power consumption and ultra low electromagnetic emission, functionally robust v.s. process, voltage & temperature variations, and secured against hardware attacks.
Reduce their time-to-market by suppressing major design efforts on clock distribution and timing closure issues.
Increase their productivity by improving the resistance of their circuits to the physical variations of the manufacturing technologies.
Tiempo asynchronous IPs are designed with standard hardware description languages (SystemVerilog functional model, Verilog gate-level netlist), are compatible with standard design flows (simulation and back-end tools) and can be directly instantiated into synchronous designs (with their asynchronous/synchronous interfaces).
Tiempo asynchronous synthesis tool, automatically compiling SystemVerilog asynchronous models into Verilog gate-level netlists, is available to the user as an optional license attached to the purchased IP license.