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Top 10 Lessons Learned about IP Management
A panel of experts from Dassault Systemes, ARM, Cadence and IPextreme turned a critical eye to the management of IP in the Google-on-Air event.
Last week, I moderated a panel on the evolving challenges faced by semiconductor companies in managing a growing base of intellectual property (IP) blocks. While the panel was sponsored by Dassault Systemes, it included additional experts from ARM, Cadence and IPextreme. What follows are my take-aways from their discussions.
Lessons Learned on IP Management
Lesson #1: There is more software than hardware IP in today’s SoCs. This realization leads to several conclusions:
- Adding related software IP to existing HW IP will require greater collaboration of design and verification teams. In turn, this will require increased management of data, libraries, etc.
- The design and integration of these software-intensive hardware systems will require more modeling and integration. Perhaps one discipline can learn from the other, e.g., the application of Agile software methodologies to the design of hardware SoCs. Or maybe the more inclusive methodologies of a systems engineering approach (see Incose) would help. More likely, a defector standard approach (e.g., product-line family, platform-based IP) will emerge from successful companies. Warren Savage was cool on this last point as he pointed out that successful companies will be reluctant to share their (IP) methodology.
Lesson #2: The IP market includes system integrators as well as semiconductor companies. This make-up reflects the evolving changes in the semi supply chain. Integration has become at least as important as design. That’s why EDA tool companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. (Reference: System Integration Requires a Shared Viewpoint)
Lesson #3: IP management tools are great at enterprise level but can smaller companies afford these tools? Michael Munsey responded with two observations. First, As IP management grows in important and complexity, smaller companies will need to find ways to fund this activity. Second, cloud-based tools will help ease the cost.
Lesson #4: Many companies provide IP design solutions. But verification IP (VIP) is becoming a bigger issue. How will smaller companies create and/or include VIP? Will you buy design IP from one provider and verification from another? (Probably not.) How will this push for verification affect the traditional design-verification flow? These questions led into a discussion about other IP processes (see #5).
Lesson #5: In addition to design and verification, process and manufacturing IP must also be managed. For example, the Internet-of-Things (IoT) technologies are revitalizing existing process nodes, i.e., 130nm analog and MEMS designs. Many of the applications will use 3D stacked dies. To be successful, costs must be kept really low by close management of the product life cycle – from design through manufacturing.
Lesson #6: The IoT presents new challenges and hence opportunities for the creation of larger IP modules, e.g. connectivity IP subsystems. One example might be the emerging Sensor Fusion Hub. “Sensors will certainly be everywhere in the IoT, so why not create a subsystem that deals with this part of the solution and ties it all together from the designer,” noted Richard Wawrzyniak of Semico Research (not part of this panel). [Reference: “Soft (Hardware) and Software IP Rule the IoT”]
Steve Brown from Cadence reminded everyone that connectivity IP will present continued challenges for digital RTL designers in the integration of analog and mixed signal systems. [Reference: “Digital Designers Grapple with Analog Mixed Signal Designs”]
Lesson #7: Security is a major concern that will grow as more companies find and productize their own IP.
- Steve Brown talked about non-disclosure agreements or NDAs as a simple security measure.
- Michael Munsey explained how protected IP is showing up in places it shouldn’t. One reason for this is the poor internal governance within corporate databases. Often, companies simply lose track of where the IP is used. There should be a managed pedigree or record of IP heritage.
- Warren Savage noted that many companies don’t know where IP is going in their own chips. Tagging of both hard and soft IP are available but work with varying degrees of success. Cloud-based systems can be hacked. But most IP is accidently used where a license ddoesn’texist. [Reference: Long Standards, Twinkie IP, Macro Trends, and Patent Trolls ]
Lesson #8: Simon Rance explained why IP management was needed to address the mega-data challenge. He noted that IP isn’t strictly about RTL-based design flows. Rather, it’s about hardware-software flows and documentation. It would be very useful to add layers of (machine readable) metadata onto the IP that’s available to most everyone. However, this would require better connectivity of IP to EDA tools.
Lesson #9: IP models will need to improve from better characterization for analog IP to inclusion of ever increasing amounts of SW models:
- Steve Brown confirmed that all of these models need to play together including hardware-software, chip-to-board, etc. Time-to-market pressures may make extensive modeling cost and time difficult for many designers. Standards might help.
- Michael Munsey said that semiconductor companies are confronting many of the same issues as faced by system companies 15 years ago. He suggested that the automotive standard ISO 26262 might serve as a good model for system-level verification in the SoC space.
- Warren Savage wasn’t so sure, noting that the semiconductor space moves too fast for the compliance-based automotive market.
Lesson #10: Design-verification methodologies and process flows must evolve to handle the quickly growing amount of IP and related mega-data volume that is coming.
This entry was posted in General and tagged ARM, Cadence, Dassault Systemes, design, EDA, enterprise, governance, hardware, IP management, IPExtreme, ISO 26262, manufacturing, mega data, patent trolls, security, Semico Research, software, subsystem, verification. Bookmark the permalink.View all posts by John Blyler