Semiconductor IP News and Trends Blog

Trend Suggests IP Development and Verification Are Pain Points

The latest results from the annual CDT survey point to changes in the reasons behind ASIC prototyping – from hardware, software, and systems to IP.

This year’s Chip Design Trends (CDT) “ASIC/ASSP FPGA-based Prototyping” (2012) survey reinforced past trends while providing a few surprises. The survey yielded much data, so let’s start with a high-level overview.

In 2012, hardware-software co-design and co-verification were again the number-one reason for ASIC designers to use FPGA-based prototypes (see Figure 1). Not surprisingly, hardware chip verification was the second leading driver, followed by software and then system verification.

Figure 1: Current and planned reasons why ASIC/ASSP chip designers use FPGA-based prototypes. Courtesy of Chip Design Trends (CDT)

A surprise came when designers were asked about future planned projects. All of the above current motivators were still there. But respondents indicated that software development would fall behind IP development and verification as an important issue. This probably means that IP development and verification has proven to be a sore spot for today’s designers.

How do these trends for 2012 compare to years past? Hardware-software co-design and co-verification remain the biggest reason for the FPGA prototyping of ASICs, followed by hardware-chip verification (see Figure 2). In 2012, software development continues to climb as an important driver while system-integration issues fall. IP development and verification has mixed results, suggesting that this factor requires further investigation. I’ll try to cross-correlate the IP trend with other data in a future article.

Figure 2: Shown are cumulative reasons for FPGA prototyping – from 2008 through 2012. Courtesy of Chip Design Trends (CDT)