Semiconductor IP News and Trends Blog
Tweets From GlobalPress, GSA, and the Pauling Lectures
The week as tweets with bird-sized bits of content covering a broad, birds-eye view of technology and science from three different events.
Here’s a summary of all of the events I attended this week – from a science lecture on disruptive science to the breadth of technology showcased at the Globalpress event and yesterday’s GSA Silicon Summit. – JB
jblyler @Dark_Faust — Past 190-nm nodes benefit from leading edge, e.g., enhanced power – Heinlein @ARMCommunity @GlobalSemi @chipestimate #semieda #semip – (20h ago)
Ethernet service revs grow to $48b by 2016 – Uday Mudio @vitesse #esummit13 #semip @chipestimate #semieda – (1 day ago)
Phone becomes game console w/ SlimPort. BT connects handset @Analogix #esummit13 #semip @chipestimate #semieda pic.twitter.com/ByNfeCIT5a – (1 day ago)
Phone becomes game console w/ SlimPort. BT connects game handset @Analogix #esummit13 #semip @chipestimate #semieda pic.twitter.com/tVdtEEVv2R – (1 day ago)
Subsystem #IP – Now need hooks among diff subsystems, integration. Rowen @tensilica #esummit13 #semip @chipestimate #semieda @Chip_Design – (1 day ago
200 global licenses with 2.4B cores in market – impressive @tensilica #IP footprint. Rowen @tensilica #esummit13 #semieda @chipestimate – (1 day ago)
#IP evolves – bazaar (pieces) to superstore (off shelf) to factory (configured). Rowen @tensilica #esummit13 #semip @chipestimate #semieda – (1 day ago)
@Algotochip IP ecosystem continues to grow with ARM, Tensilica-Cadence and others. #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
@IntelSys #embedded SW tools open? Not Eclipse based, but have plugins. #esummit13 #semieda #semip @chipestimate @Chip_Design
Power of less concern than performance for #embedded SW dev – @VDC_Research @IntelSys #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
Intelligent #embedded sys must connect to world – Hinstorff @IntelSys software #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
“Watts? Joules?” SW developer power dilemma says Glenn Perry @mentor_graphics #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
RT @Nu3dPrinters: @Dassault3DS: #3DEXPERIENCE Customer Forum China 2013 #3DXforum 3ds.com/company/events… pic.twitter.com/rowcau0fbo” – (2 day ago)
“Most system delays come when HW and SW integrated.” Rhines, @mentor_graphics #esummit13 @Portland_State #semieda #semip @chipestimate – (2 day ago)
Emb sw dev headcount surges every node – 17x between 90 to 14 nm. Wally Rhines, @mentor_graphics #esummit13 #semieda #semip @chipestimate – (2 day ago)
Customer Specific Standard Products focus on mobile subsystem, programmed @quicklogic #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
Measuring pressure of fly (3Pa) possible with electronic skin. Zhenan Bao @Stanford #esummit13 #semieda #semip @chipestimate @Chip_Design – (2 day ago)
IP integration w IPExact packager + smart subsystem creator. Vivado @xilinx Tom Feist #esummit13 #semieda #semip @chipestimate @Chip_Design
Green computing Calxeda uses @ExarCorp power management for ARM-based microservers. #esummit13 #semieda #semip @chipestimate @Chip_Design
From fish eye to panoramic view w zero content loss – Geo Semi #esummit13 #semieda #semip @chipestimate @Chip_Design pic.twitter.com/bSjMKo7A7u
@Stanford Yi Cui at #esummit13 – Can paper industry be saved w nanotube-embedded, paper batteries? #semieda #semip @chipestimate.com
TV turner fabed at 55 nm. Sweet spot for RF and digital, via Silicon Lab’s Stansberry at #esummit13. @silabs #semieda #semip @chipestimate
@altera advances high speed optical network IP by acquiring Danish TRACK via Vince Hu #esummit13 #semieda #semip @chipestimate @Chip_Design
ARM still strong partner even with Intel 14-nm finfet fab word, says @altera Vince Hu #esummit13 #semieda #semip @chipestimate @Chip_Design
Antenna freq tuning w MEMS caps ups gain by 1.3 dB or 35% via Yost Cavendish Kinetics #esummit13 #semieda #semip @chipestimate @Chip_Design
ARM still strong partner even with Intel 14-nm finfet fab word, says @altera Vince Hu @esummit13 #semieda #semip @chipestimate @Chip_Design
@altera advances high speed optical network IP by acquiring Danish TRACK via Vince Hu @esummit13 #semieda #semip @chipestimate @Chip_Design
TV turner fabed at 55 nm. Sweet spot for RF and digital, via Silicon Lab’s Stansberry at @esummit13. @silabs #semieda #semip @chipestimate
@Stanford Yi Cui at @globalpresspr – Can paper industry be saved w nanotube-embedded, paper batteries? #semieda #semip @chipestimate.com
“All science is either physics or stamp collecting.” – Rutherford @InstforScience @chipestimate @SemiEDA @eda @terrybristol
ISEPP Lecture – Dr. Dupree – Myth 1: Science discovers true divisions in world. @InstforScience @chipestimate @SemiEDA @eda @terrybristol
ISEPP: The Hunt for Earth 2 – A Shower of Kepler Planets! bit.ly/10QSEgN @InstforScience @chipestimate @terrybristol @SemiEDA @eda
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View all posts by John Blyler
JB, it’s nice to hear that Wally Rhines (CEO of Mentor Graphics) agrees on integration of HW and SW being a major source of project delay. The traditional electronics product development cycle sees the hardware and software being developed on separate tracks, with software starting later when hardware becomes better defined, and real or virtual prototypes become available to use. But weeks or maybe months later, the two are integrated and often the software must be tweeked (sometimes a lot!) to work with the given hardware … worse, the hardware may need modifications which introduces a long iteration loop.
At Space Codesign, our SpaceStudio software supports true hardware/software co-design … not just accelerating the hardware design (the original intent of ESL) with software development tools bolted on, then long iterations between the two. SpaceStudio includes automated support for hardware/software partitioning in architectural exploration, where functions can be retargeted for hardware (as a co-processor or accelerator) or software implementation (as a software task running on a processor, which includes an OS or at least bare metal) using the same C/C++/SystemC model without recoding. Candidate architectures can be taken to FPGA prototyping and even a final FPGA design (if that is the case). 🙂