Semiconductor IP News and Trends Blog

Verification IP Faces Hardware and Software System Challenges

Design and verification IP must evolve to enable the full integration of hardware and software subsystems.

Verification intellectual property (VIP) has benefited from both EDA and IP growth. As Ed Sperling reported recently on System-Level Design, the highest growth reported (for 4Q2011 in EDA) was in physical design and verification, which grew 30% year over year to $392.4 million. IP revenue also grew 13.4% to $432.2 million. The growth of both EDA verification tools and IP in general bodes well for verification IP.  

What has spurred this growth? One reason is that System-on-Chip (SoC) designers rely increasingly on IP reuse – especially interface IP – to meet both increasing design complexity and shorter time-to-market product cycles. But hardware IP must be verified at the component level and then verified once again after integration to the overall system, which drives the need for additional VIP.

Another factor in verification IP growth is the increasing use of design IP over stand alone chips to increase functionality of the SoC block. This is especially true for interface and bus IP, which is tightly integrated with corresponding software protocol IP like device drivers. Thus, verification is needed for both the hardware and related software IP to form a reliable interface subsystem. This trend is a natural evolution of component IP to subsystem blocks and even higher-level system IP.

When asked how this move toward a system context will affect the growth of intellectual property, Neil Hand, marketing group director at Cadence, put it this way: “And once that (software and firmware IP issues) gets solved, the next thing is how you build that (IP) into the system level models and supply chain models … But we’re at such a low level on the IP side that there’s a lot of integration that has to happen.”  

Indeed, a great deal of integration issue lie ahead as component IP evolves into subsystems consisting of both hardware and software firmware. Fortunately, these challenges are being resolved, thanks in part to the hardware “awareness” of firmware, device driver software and even operating systems.

The challenge really begins with the incorporation of system-level, hardware “unaware” software applications as in the end-user consumer space. Merging these two great intellectual property domains – hardware and software application – will not be easy. Complicating matters is that hardware and software engineers speak a different language while using the same words.

Add to this enormous challenge the fact that user experience will drive many future designs. This means that a real-time, end-user feedback loop will need to be developed and maintained through the SoC engineering development process. Software application engineers are familiar with this approach. Silicon hardware engineers are less so. 

Verification remains the one constant throughout all of these hardware-software evolutionary integrations. But verification will need to change and adjust to the coming user driven development methodology. Several pundits have acknowledged the need for VIP changes, though each from a differing point of view. For example, Faisal Haque, Sr. Director of Engineering at Qualcomm, stated that VIP architecture had to be revisited and redesigned for scalability and customization. “We must stop adding code to already bloated VIP and go back to basics,” said Haque. (see, “Verification Complexity Driving Innovation in VIP”)  

Design and verification IP must evolve to enable the full integration of hardware and software subsystems.