Semiconductor IP News and Trends Blog

Verification IP is not IP Verification

Is it possible to find a modern SoC design that doesn’t contain numerous IP cores, from logic and memory to interface IO? It would be nearly impossible to create timely, cost effective SoCs without such IP.

Today, most chip designers are comfortable using someone else’s core blocks as long as that IP can be verified.  Typically, this means confirming that the IP works properly by performing all of the functions that are expected of that IP. Over the last several years, an entire sub-market has developed to provide verification IP (VIP).

Unlike design IP, which becomes a part of the actual SoC, verification IP blocks become part of the test bench. Both the design and verification IP markets have matured to the point where most designers can safely assume that IP purchased from reputable sources will verifiably function as advertized. (Although global IP concerns still exist: see “DAC Panel Explores IP Theft in Global Markets)

The other aspect of verification IP is in compliance testing. For example, designers want to be sure that a USB 2.0 controller IP core meets the requirements of the USB 2.0 specification. By and large, these are minor concerns as long as the IP is procured from a reputable vendor.

Today, design and verification IP are common in SoC designs. The big challenge with IP has shifted from block-level to system-level concerns, as I was recently reminded by Paul Lindemann, Marcom Manager at CAST.  “The problem with using IP lies not with the IP itself but with the design incorporating the IP.” Designers want to verify the operation of the IP block within their unique design. This is why they are anxious to learn about the experiences of others who have used the same IP.

Consider the case where multimedia functionality is needed in a SoC. The project designer may choose to add a JPEG image compression IP block, especially if there is not in-house expertise in that area. Once the correct design IP is selected and verified, the next big concern is how that IP will function within the system, e.g., with the existing memory interfaces, bandwidth performance, etc.

One way to verify the operation of the design IP within the SoC is to run a simulation program. That is why most vendors supply bit accurate models (BAM) with their IP. Often, BAMs will be provided  during pre-sales so a potential customer can see how the IP will work on their unique chip design.

BAMs are used to transition from a algorithm model to a more hardware accurate model. While an algorithm may run well on Mathlab, a more precise hardware specific model is usually required to verify operation on a specific hardware device. The output of a bit accurate model exactly matches the corresponding bits of the proposed hardware.

Verification IP blocks and verifying the functioning of IP within a SoC are two different things. The former is essential for the IP market to exist. That later is essential for the IP market to continue to evolve and grow.