Semiconductor IP News and Trends Blog

Verification Perceptions

A panel on the SoC verification gap leads to ongoing discussions about the pain threshold and maturing attitudes toward emerging standards and inefficiencies.

It turned out that the DVCon panel was just the tip of the iceberg for opinions about the reality of an alleged verification gap in the design of system-on-a-chip (SoC) platforms. What follows are the highlights from the panel and related conversations with Amiq, Synapse, and Jasper. –JB

Panel: “Did We Create the Verification Gap?”

According to industry experts, the “Verification Gap” between what we need to do and what we’re actually able to verify for large designs is growing worse each year. According to these experts, we must do our best to improve our methods and tools before our entire project schedule is taken up by verification tasks.

There were great comments made by the panelists, which will be covered in the next few weeks. In the meantime, here are a few tidbits to ponder from my pre-panel interview:

“Are we blindly following industry best practices…” –JL Gray, Senior Architect, Cadence

“…We have to expect to provide a means to make in-field changes…” –Bill Grundmann, Fellow, Xilinx

“There needs to be more focus on integrating and verifying the SW modules with HW blocks…” –Mike Stellfox, Fellow, Cadence

“Many design teams are looking for a single hammer that they can use to address today’s verification challenges.” –Harry Foster, Chief Verification Technologist, Mentor Graphics

“Balancing resource and budget for a product must be done across much more than just verification.” –Jim Caravella, VP of Engineering, NXP

“The conclusion of this panel seems to be that a verification gap does exist in varying degrees. Only when the gap is large (i.e., the pain of verification is great and affecting the project return-on-investment [ROI]) does this gap become a problem.” –John Blyler, Moderator

Christian Amitroair, CEO of Amiq, talks with John Blyler.

Amiq

Christian Amitroair, CEO of Amiq, had several germane observations about the verification gap. He thought that the gap was more a matter of attitude. “Until recently, verification has been a second-class citizen in comparison to design,” notes Amitroair. “Years ago, when Verisity (acquired by Cadence in 2005) first came out with the e-hardware verification language, it was a real milestone. It changed everyone’s perspective about verification, although many engineers didn’t like the new language. That was probably because it was a new language and it wasn’t register transfer level (RTL). Verification takes a different tool suite and mindset. Also, that early verification language set the stage for the Universal Verification Methodology (UVM). So, attitudes about verification have changed in the last decade or so.”

Synapse

Satish Bagalkotkar, President and CEO of Synapse Design Automation

Most people agree that SpecMan – the tool that supports the e-verification language – as well as UVM and Verilog have created big shifts in the way people think about verification.

Ongoing changes have further moved verification into the early stages of the design process. Satish Bagalkotkar, President and CEO of Synapse Design Automation, notes that UVM now has a transaction-level-modeling (TLM) 2.0 interface for higher-level development. This integration enables advanced verification and modeling techniques via virtual prototyping with SystemC/TLM 2.0.

Still, Bagalkotkar acknowledges that a critical gap does exist between RTL verification and system-level modeling. His company claims to have bridged this gap by creating virtual platforms using TLM 2.0 and integrating these models into a SystemVerilog/UVM-based verification methodology.

Jasper Design Automation

Kathryn Kranen, President and CEO of Jasper, talks with John Blyler.

Is there a verification gap? Or is it that too much time is being spent inefficiently on verification? Kathryn Kranen, President and CEO of Jasper Design Automation, believes the latter. Customers have told her about too many wasted simulation, engineering, and debug cycles that are being spent to achieve the desired levels of design quality.

“One solution is to offload the simulation and certain aspects of functional verification from large monolithic regressions,” explains Kranen. For example, low-power verification is done today to capture the effects of multiple-power domains in an SoC. Engineers are offloading that low-power verification task from the larger, system-wide verifications tasks.

Kranen believes that the verification gap is less about an excess of verification and more about an excess of time spent on verification.

Verification Interview

Cadence’s resident journalist-celebrity, Brian Fuller, talked with JL Gray and John Blyler about verification hot topics. Look for that video to be released in the next few months.