White Papers

Reducing Switching Power with Intelligent Clock Gating

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% in Virtex®-6, Spartan®-6, Kintex™-7, and Virtex-7 FPGA designs.

To see the entire IP Doc from Frederic Rivoallon, Xilinx, please log in or register.