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← Images from Sonoma Indy Race
Only a small portion – but certainly the most critical – of all the available sensor data is displayed during a race.
IP compliant to the NVM Express 2.0 specification for high performance PCIe SSD
SMIC 90nm 9T Standard Cell Library - HVT, 1.2v operating voltage
simple access to PCIe NVMe SSD of the market
SMIC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications
eSPI & SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus)