In the first of this blog trilogy, Talking Sense with Moortec… ‘Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. There’s a Japanese … Continue reading »

As the de facto IO interconnect technology, PCIe has commendably addressed the performance bottleneck at the IO interface by doubling the bandwidth support every 3-4 years over the course of 5 generations of the specification and with Gen 6 at … Continue reading »

Since 2013, we have seen the HBM specifications being released by JEDEC and companies announcing in the same month HBM products just like magic. How can these companies have a silicon-proven product altogether with newly announced official specifications? What is … Continue reading »

It almost doesn’t matter what your job may be, whether in the public sector or a private company, or how technical or how dangerous, many of life’s adages and sayings can be interpreted to have some direct meaning for all … Continue reading »

As you may have read in our previous blogs, chip designers working on advanced nodes now typically include a fabric of sensors spread across the die to address a number of very specific challenges. In this, the final instalment of … Continue reading »