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Will Discrete IP Threaten the Subsystem Market?
Projected growth in the third-party semiconductor intellectual-property (IP) market through 2017 may affect the direction and evolution of subsystem designs.
Earlier this week, Semico Research issued a report predicting that the compound annual growth rate (CAGR) for the third-party semiconductor-IP (SIP) market would exceed 19% from 2013 to 2017. To understand more, I asked specific questions of Rich Wawrzyniak, Senior ASIC and SoC Market Analyst for Semico Research. What follows is his response.–JB
[Blyler] Does this increase in third-party SIP revenues help or hinder the development of IP-subsystem packages?
[Wawrzyniak] This is a very interesting question, and the answer can have far-reaching implications for many companies – both IP vendors and users. In Semico’s view, the growth in revenues for the discrete third-party SIP market is nothing new. It has been occurring for some time, driven by the rise in complexity in system-on-a-chip (SoC) silicon solutions. More designs are being done using the SoC design methodology. And in those designs, more IP is being used. This rise in device complexity accounts for the growth in the IP market.
The IP-subsystem market is just emerging – again, being driven by the rise in SoC complexity. SoC design costs for silicon and software are also rising. For the first time, in 2012, software design costs outstripped silicon design costs. SoC designers are looking for ways to reduce the level of effort and cost they need to expend in order to create these complex silicon solutions. At the same time, they want to increase functionality and performance. IP subsystems are the means to accomplish that task.
At the current time, I do not see anything on the SoC-design landscape horizon that will markedly reduce the level of effort that designers are expending – except the use of IP subsystems.
So will growth in the discrete-IP market hinder or delay growth in the IP-subsystem market? Semico does not believe so, as we are in the very early stages of IP-subsystem market development.
(Toward this question and others, Semico is hosting a conference on the IP ecosystem at the Double Tree Hotel in San Jose on November 6. We will be addressing this question and more – all related to the central issue of IP market direction and evolution. You can find more information about our conference here.)
One common thought circulating about the development of the IP-subsystem market is that its growth will cannibalize the revenues of the discrete-IP market. We at Semico do not believe this to be the case. The reason lies in why the IP-subsystem market is developing in the first place.
We need to remember that the larger semiconductor companies – say the top 15 to 20 – have been internally developing their own IP subsystems in the form of system-level functions for the last several years. Now, this concept has migrated over to the discrete-IP market, and we see several IP vendors developing and deploying their own products into the marketplace.
Why did designers at the top-tier semiconductor companies do this to begin with? As design complexity and costs increased, they sought ways to reduce the level of effort they were expending to create these system-level functions out of discrete IP blocks. They reasoned it was much better and more efficient to deal with the design efforts in larger pieces instead of trying to spend the same effort acquiring, managing, and integrating 200+ discrete IP blocks into their designs. Because the IP subsystem is one complete, contiguous system-level function in the form of one block, it can be reused much more easily than trying to disaggregate and then re-aggregate multiple IP blocks that make up that system-level function. The IP-subsystem concept was born.
The following chart makes it easy to see why this is happening. This chart was developed from other research Semico has conducted on the ASIC and SoC design-starts landscape. It looks at the average gate-complexity level by device type over the last 11 years with a 5-year forecast. This specific chart looks at the average gate count in three types of SoCs. It is driven by looking at the use of these SoCs in 70 end-market applications. So it is the number of designs for each product type – in all the applications we track – multiplied by the gate count in each part type, and then averaged across the total for each year.

Figure: Forecast for the average gate-complexity level by device type. (Courtesy Semico Research Corp.)
The spike in the growth rate from 2002 to 2007 is caused by more designs switching over to the SoC design methodology. Because it is coming from a small base, the growth rate at the beginning is high. It declines around 2008 due to the impact of the “financial meltdown.” (Designs put on hold or cancelled outright equaled fewer designs being done in this timeframe.) Even with the reduction in the number of designs, the growth rate was still positive.
Then, starting in 2011 – after the markets stabilized and had started to recover – gate-complexity growth rates started to increase once more. The forecast years of 2013 to 2017 see a pickup in growth rates in response to increased transistor budgets, which were made possible through use of the newer process geometries and the continued need for more functionality. In this case, functionality drives complexity. This, in turn, drives the use of more IP and eventually, the evolution of the market to the use of IP subsystems.
As an aside to this chart, it’s important to note that from 2008 to 2010, many architectural refreshes (as embodied by first-time design efforts) were put on hold until the market showed signs of recovery. This was due to the fact that most companies will take the opportunity presented by a first-time design to invest the most time, effort, and money in developing the architecture they want to carry them for the next two to three years. The financial meltdown forced many companies to curtail these efforts and stretch these architectures further than they would have liked. Now that these efforts restarted toward the end of 2011 and into 2012 and 2013, there is a great deal of ‘catching up’ to do. That means the use of even more IP to provide the functionality needed in these new designs: again, another solid driver for the IP market.
Semico doesn’t see this trend ending anytime soon. Consumers of electronic devices – whether mobile or stationary – are asking for more connectivity and the feature sets to take advantage of that connectivity. This means more complexity in the solutions powering these devices. Given this trend, it is easy to see why IP market revenues are growing and – given the increase in design costs – why the IP-subsystem market will continue to gain importance over time.
[Blyler] Thank you.
Look for Part II of this story in my next blog.–JB
This entry was posted in General and tagged ASIC, discrete, ecosystem, forecast, gate complexity, IP subsystem, Richard Wawrzyniak, Semico Research, semiconductor IP, SOC, third party. Bookmark the permalink.
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