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About the Author

Lana Chan is a Director of Product Engineering at Cadence Design Systems, responsible for the PCI Express Family (PCIe, CXL, CCIX Transport), Storage Interface (NVMe, SAS, SATA) and Display Port Verification IPs at Cadence. She is passionate about defining and developing verification solutions that address customer's time to market requirements as well as their overall user experience. Prior to joining Cadence, Lana did 10+ years of hands-on ASIC and FPGA digital design and verification development of PCI Express IPs and various other high speed protocols macros in a wide range of industries.