Semiconductor IP News and Trends Blog

IP Suppliers and Design Houses Get Tighter

ARM’s acquisition of Prolific highlights the challenges between designers and builders at the leading edge process nodes. Will this trigger a new round of M&As between EDA-IP vendors and perhaps even fabs?

Everyone concedes that designing and fabricating complex System-on-Chip (SoC) devices near the 20nm process node and below will be tough. One way to deal with the problem is to enhance the integration between the designers and builders of chips. This seems to be the main reason for ARM’s acquisition of Prolific, a chip design services company. Such an acquisition should strengthen ARM’s physical IP position – including logic, embedded memory and interface cores – at the more troublesome lower nodes.

Will other IP providers, perhaps in the EDA tools market, follow suite with similar acquisitions? Judging by his recent blog, long time industry pundit Gabe Moretti thinks this might just be the tip of the iceberg.

Gabe provides convincing arguments for future acquisitions similar to ARM’s purchase of Prolific. He conjectures that Synopsys’s growing strength in the IP market might justify the purchase of an IP core supplier like MIPS.  “After all, having purchased the analog portion of MIPS, why not finish the job,” teases Gabe.

Another possible IP-plus-design services marriage might be Cadence’s potential purchase of eSilicon. As Gabe puts it, Cadence would not only acquire further expertise in design creation and development, but would also, “get Jack Harding back as its CEO freeing Lip-Bu Tan to pursue strategic investment opportunities on a full time basis.” I think that Cadence’s Senior VP of R&D, Chi-Ping Hsu, might have other thoughts on this last speculation.

Another possible scenario is one that has been raised may times in the past, namely, that a major foundry would acquire one of the big three EDA vendors. Peggy Aycinena committed this speculative idea to print many years ago. Such a union between foundry and EDA tool supplier should provide the tightest of development and manufacturing arrangements. Why hasn’t such an acquisition or merger ever taken place?

I attempted to answer that question years ago, suggesting that the way to judge such mergers was to focus on the lowest common denominator – namely, the IP. (see, “Are EDA and Semiconductor Markets Cycling Back or Spiraling into the Future?”)  At the time, I meant IP to include everything from both hard and soft design IP to process data IP. Here is what I found:

“They (sources) saw it as an interesting twist that foundries like TSMC are starting to come out with their own intellectual property-in essence, competing with their own partners. This is perhaps understandable, as foundries like TSMC strive to differentiate themselves from commodity wafer providers. Still, foundries that offer IP-are becoming more like ASIC vendors. At some point, they could conceivably sell standard products. They would then become a new generation of chip companies. Although my sources were not sure that it will go that far, other developments certainly suggest a chance for the ASIC business model for smaller-geometry chips.”

“For example, consider the rise in DFM and DFY tools at 90 nm and below. As designs move into smaller and smaller geometries, the EDA tools have to be more tightly coupled to the process technology. The most efficient way to achieve that goal is to have the foundries that have the manufacturing facility. As noted earlier, however, there will be fewer and fewer fabs at the 45- nm level and below. The few remaining fabs like TSMC will therefore have to deliver very detailed and robust process data to the EDA vendors or provide the tools themselves. “

“This latter scenario has fired up the imagination of many observers. First, non-commodity foundries offer design blocks and IP. Next, these same foundries start to own the tool chain by offering the greatest DFM-DFY tools for their own processes. Suddenly, the cycle started 15 years ago is complete. Then, the only companies making the EDA tools were the big IDMs like LSI. “At that time,” one of my sources mused, “LSI had the biggest internal CAD group of any other company.” Now, that dubious honor is held by IBM and Intel. “But,” my source added, “I talk to Intel almost every week, and they tell me that they’ve got these directives to use more external tools.” Developing and maintaining internal tools at 65 nm and below is just too expensive-just like building a new fab. Bingo. From IP to tools to fabs. “

“Where will it end? Will the cycle just repeat itself? It probably won’t, which is why I prefer the analogy of the spiral in which the cycle ends at a new set of end points. My sources believe that those new boundary conditions will be marked by the commercial realization of nano- and quantum-computing. “Maybe in another 10 years or so, all this silicon stuff will just be old news,” one suggested. If the last 20 years are any indication, he’s probably right. In that time period, the semiconductor industry successfully created chips from 10 microns down to 65 nm. One can only guess at what the market landscape will look like at the end of this spiral.”