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DesignCon 2012 – More SI, Less EDA

This year’s DesignCon show focused more on board-level signal intregity and testing issue than on chip design and verification.

DesignCon has changed over the years. It started as a board-level interface show. In recent years, a large chip-level Electronic Design Automation (EDA) and verification component was added (see references for past coverage of the show). This year, the EDA tools component was greatly diminished as the show returned its roots, although with a much stronger emphasis on board-level testing, debug and signal-power integrity issues.

As usual for an editor, I spent more time in meetings that actually walking the show floor. Still, there was plenty to catch my eye when I did wander onto the exhibition hall. Here is a brief summary of my meetings and show floor highlights from Designcon 2012.

Heat-sink Antennas

My first meeting at the show was with Martin Timm, marketing director at CST. Martin, who holds a doctorate in EE and accelerator physics, is always a wealth of information. During the course of our conversation about various paper sessions at the show, he commented about on session that highlight the unintended consequences of a heat-sink design.  Typically, a heat-sink designed to suppress EMI will be grounded to the board. But this approach requires additional space while increasing both routing complexity and cost. A proposed new heat-sink design uses hat-like side walls that purportedly save on board routing space, complexity and costs. (see, “Investigation of High Speed SerDes Induced EMI and its Suppression with Novel Heatsink Design”)

Martin Timm from CST.

Unfortunately, the shape and conductive characteristics of the heat-sink design made it operate as an electromagnetic resonator (5 GHz antenna) for high-speed SerDes signals. Naturally, Martin pointed out that this affect could be easily modeled with CST tools.

[Side note: I recently wrote about the transmission of wireless power. Martin’s comments concerned a heatsink that also acted as a wireless antenna, i.e. it serves as both a radiator of thermal and electromagnetic energy. Could the two functions be combined? Probably not, since the properties of each type of radiator seem to be completely different. Still, it might be worthy of investigation for a future show.]

Another observation by Martin was the importance of time domain analysis to digital designers, while EMI specialists prefer the frequency domain. While nothing new, this observation was a common theme throughout the show.

The real world is measured in the time domain. However, the mathematical construct known as the frequency domain provides faster solutions to eye closure problems in the world of signal integrity (SI). An open eye pattern corresponds to minimal signal distortion. A closed eye pattern signifies SI problems, e.g., signals that are too long, short, low, noisy or poorly synchronized with the system clock.

Several tool announcements at DesignCon centered on the simplification of frequency domain tools so they could easily be used by digital designs – the ones who prefer working in the time domain. These ease of use improvements help to eliminate the need for an EMI (often PhD) specialist when testing and debugging signal integrity issues.

Finally, my discussion with Martin moved to the similarities between the simulations of particle accelerators to microwave systems. Particle accelerators use microwave fields to propel charged particles to high speeds. Simulation tools, like CST’s Particle Studio DIO, provide analysis of charged particle dynamics in 3D electromagnetic fields. Of course, designers need the hardware horsepower to optimize these simulation tools. (see, “How Does Intel Interconnect Many Integrated Cores (MIC)?“)

As interesting as were these side discussion with Martin, he eventually had to point out the recent signal integrity (SI) and power integrity (PI) improvements made to CST’s PCB Studio 2012.  I was particularly interested in the power measurement improvements, which included IR-drop solver that maps out the current distribution and voltage drop on multilayer PCBs and packages.

Thermal-Power Co-Simulation

At Designcon, Mentor Graphics announced a 3D full-wave field solver and integrated thermal-power co-simulation tool suite for board designers. It’s true that very few designs need a 3D full-wave solve run across the entire PCB. But the growing popularity of multi-GHz SerDes interconnects, such as PCIe-Gen 3, does require 3D modeling to deal with discontinuity effects caused by structures, like connectors, vias and some complex packages. For example, most 5GHz PCIe-Gen3 vias with ground stitching need 3D analysis.

Keeping with the unofficial theme of Designcon vendors for friendlier interfaces, the improved Hyperlynx tool offered an ease-of-use interface so that time-domain digital designers could view and optimize frequency domain issues such as signal integrity.

Current density of a high-pin count PCB.

Mentor’s announcement also had a power integrity component. Today’s ICs are designed for low power, which means they are sensitive to voltage and current swings. This sensitivity is manifested as greater complexity of board designs. Among other capabilities, HyerLynx PI predicts areas of high DC current density which can lead to hot spot temperature rises (see figure).  Why is heat such a problem?

Excessive heat can cause de-lamination and fusing of the PCB. Further, heat raises the resistance of the Cu traces which can lead to reduced voltages, thus degrading signals that lead to greater SI issues.

These power integrity concerns are compounded by thermal issues from other heat generating boards, usually in an enclosed space. Current density tools predict thermal issues centered around ICs and traces on the board. But thermal analysis shows temperature variations associated with the entire board. That’s why HyperLynx now combines both current density (Zealand acquisition) and thermal flow (Flowtherm acquisition) into one tool. This tool provides both analysis and “what-if” trade-off capabilities that suggest workable solutions.

Integrating power integrity and thermal enables greater accuracy.

Testing Serial Interfaces

At Agilent’s press event, Ross Nelson – general manager of Digital Debug Solutions – discussed challenges facing mobile computing design and test. The premise of his talk was that down-deploy of PC technology to a mobile platform is no longer an option. Instead, mobile computing had to deliver the same performance as PC-server systems but be optimized for low power, low cost and low profile.

Ross Nelson from Agilent.

This requirement has created a new set of digital and RF standards such as MIPI, MHL, LPDDR and DigRF. For example, a MIPI PHy physical layer device can deliver up to 5.8G at only 1/10th of the power required for PCIe 3.0. Not surprisingly, these standards have unique test and measurement challenges.

One of these challenges stems from the disappearing front-side busses on today’s SoCs, thanks to the incorporation of embedded memory and interface controllers. The solution seems to be a separate debug port.

Later that day, I met on the show floor with Barry Alcorn, a program manager at Agilent. He noted, as had others (see above) the need for time-domain digital designers to have easy-to-understand data from the frequency domain, e.g.,  S-parameters. This is one reason why Agilent’s Eesof EDA tools have been incorporated into many of the company’s oscilloscopes, logic analyzers and other test equipment.

AWR’s Fit with NI

I caught up with Sherry Hess over coffee. She is the VP of Marketing for AWR, which is now part of National Instruments (NI). How had the NI acquisition had effected AWR? She said that the fit was a good one, since AWR not only brought RF-Microwave design expertise to NI but also helps address many of the testing and verification issues common to the right-hand side of the Vee-Diagram.

Sherry Hess from AWR.

What was new at AWR in terms of application markets? Sherry explained that the company was reaching into a variety of segments, including agricultural, medical and automotive. The growth of electronics in the agricultural market has been observed by serveral venture capitalists – “Venture Capitalists see Major Investing Changes.” The later, namely the automotive market, is one that Sherry believes may have missed the window to capture the infotainment device business. Apple’s ubiquitous iPhone, iPod, iTablet and I-YouNameIt devices seem to have taken over that space. All that automotive manufacturers can do now is to add a plug for your i-Device.

Confirming what others have said, Sherry acknowledged the importance of user-friendly tools that bring importance analysis from the frequency domain into the more familiar time domain used by digital designers.

Mark LaPedus and John Blyler at Designcon 2012.

There were several well attended panels at Designcon which I could not attend. Mark LaPedus, senior edit for the “Semiconductor Manufacturing and Design” (SemiMD) portal, did a great job of covering both the Microsoft keynote and a analog panel:

Walking the Show Floor

Toshiba's Qosmio F750 series glasses-free 3D video laptop.

During my brief visit to the exhibitor hall, I talked with Ashraf Takla, President and CEO of Mixel, a company that specializes in mobile mixed-signal intellectual property (IP). The company was demonstrating the incorporation of their serializer and de-serializer (SerDeS) technology into the Toshiba’s first glasses-free 3D video laptop.

Mixel’s focuses on mobile physical level IP such as serial interface like MIPI and LVDS. The company is a strong proponent of Mobile Industry Processor Interface (MIPI), which follows the mobile trend to move from parallel to serial interconnect.

Mike Dini of the Dini Group.

No visit to a board-level conference would be complete without seeing Mike Dini, the ever enjoyable president of the Dini Group. At DesignCon, Mike was highlighting his “Godzilla’s Bad Hair Day” board, which was designed for high performance computing (HPC) using Xilinx’s Kintex-7 series FPGAs with DDR3 memory and 4-lane PCIe (Gen2). Other products on display contained equally monstrous code names, like Godzilla’s Son-In-Law (ASIC prototyping engine featuring Xilinx Virtex-6); Godzilla’s Destructive Electric Toothbrush (high-speed serial IO daughter card); and Godzilla’s Misbehaving Liver (10/100/1000 Base-T Ethernet card). Mike’s on a rampage with these names!

Dale and Tim from Intercept Technology.

The popular video guru from IBSystems – Graham Bell - snapped this picture of me with the folks from Intercept Technology, Inc.; Dale Hanzelka (left) and Tim Haag (right). I didn’t realize the Tim was from Tualitin, OR, near my part of the Silicon Forest. The company is a supplier of PCB, Hybrid, and RF design and layout software.

Figure: David Blaza, VP at UBM, moderates a social media panel.

At the end of Wednesday’s (2/2/2012) event, I was able to attend (thanks, David) a UBM event titled, “From Social Media to Social Learning“. This was billed as “a special evening event created for marketing and PR leaders in the electronics industry.”  This panel turned out to be a roadmap of a very bold social media experiment that will grab everyone’s attention at the upcoming DesignWest conference – formally the Embedded System Conference (ESC). I’ll cover this highlight of this important presentation in the future.


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About the Author

John Blyler

John Blyler writes the “IP Insider” blog at Chipestimate.com. He covers today’s latest high-tech, R&D and even science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist, author and professor who continues to speak at major conferences and before the camera on . John is the Vice President, Chief Content Office for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and others. He holds a BS in Engineering Physics and a MSEE. John plays the piano and holds a black belt in TKD.