Semiconductor IP News and Trends Blog
Follow our semiconductor IP Insider blog section for up to date information on the latest technological advances in silicon IP
September 10, 2019 - By John Blyler
Will a single source of truth help multi-discipline and multi-domain engineers connect the dots for system-of-system development? Continue reading
September 8, 2019 - By Neelabh Singh
Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. … Continue reading
August 24, 2019 - By Thenmozhy Kaliyamurthy
The demand for higher resolution displays is exploding across the market segments from electronics like television, monitors, laptops, and smartphones to the emerging technologies like video and vision, automotive, and AR/VR. The bandwidth requirement for displays increases multi-fold with higher … Continue reading
August 16, 2019 - By Sharon Rosenberg
At this point, you’ve probably heard about the Accellera Portable Test and Stimulus Specification (PSS). You may even have heard a user passionately describe how the PSS revolutionized their flow and how it shortened timelines in a project much like … Continue reading
August 5, 2019 - By Jai Durgam
In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP for both vendors and consumers of IP. In May 2019, Silvaco was awarded a patent for System and Method … Continue reading
July 23, 2019 - By Sumit Dalal
PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations. Aligned with this, Synopsys also announced the collaboration of its Design and Verification Solutions with Astera … Continue reading
July 22, 2019 - By John Blyler
The Design and Verification Conference and Exhibition (DVCon U.S.) held earlier this year once again brought chip developers together with EDA tool vendors to tackle major issues. Continue reading
July 2, 2019 - By Paul Mclellan
There are two famous parties in the EDA world. The Denali Party by Cadence, of course. I’m afraid you missed that one for this year—it is always on the Tuesday of DAC. The second one is the HOT Party organized by … Continue reading
June 5, 2019 - By John Maneatis
I reviewed John Cooley’s Deepchip article titled ‘Movellus beats out True Circuits PLL/DLL IPs as #9 “Best of 2018″‘ (http://www.deepchip.com/items/dac18-09.html) and found it quite entertaining. The article suggests that Movellus has us all beat (e.g. TCI, AB, SC). In fact, … Continue reading
June 5, 2019 - By Sharon Rosenberg
Busy and exciting times for the Cadence PSS team and I stepped out of the routine to write something about it. We just finished a successful evaluation at TI Israel. A power verification and validation team introduced to us a … Continue reading
